perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events up to the RC_ST_SPEC (0x91) event with the exception of: - L1D_CACHE_REFILL_INNER (0x44) - L1D_CACHE_REFILL_OUTER (0x45) - L1D_TLB_RD (0x4E) - L1D_TLB_WR (0x4F) - L2D_TLB_REFILL_RD (0x5C) - L2D_TLB_REFILL_WR (0x5D) - L2D_TLB_RD (0x5E) - L2D_TLB_WR (0x5F) - STREX_SPEC (0x6F) Create an appropriate JSON file for mapping those events and update the mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that file. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sean V Kelley <seanvk.dev@oregontracks.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging) Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>hifive-unleashed-5.2
Florian Fainelli
Arnaldo Carvalho de Melo
parent
93fe8f1e11
commit
7025fdbea3
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@ -0,0 +1,179 @@
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[
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{
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"ArchStdEvent": "L1D_CACHE_RD",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR",
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD",
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_CLEAN",
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL",
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD",
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD",
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM",
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN",
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_SHARED",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_NORMAL",
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},
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{
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"ArchStdEvent": "BUS_ACCESS_PERIPH",
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},
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{
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"ArchStdEvent": "MEM_ACCESS_RD",
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},
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{
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"ArchStdEvent": "MEM_ACCESS_WR",
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},
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{
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"ArchStdEvent": "UNALIGNED_LD_SPEC",
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},
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{
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"ArchStdEvent": "UNALIGNED_ST_SPEC",
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},
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{
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"ArchStdEvent": "UNALIGNED_LDST_SPEC",
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},
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{
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"ArchStdEvent": "LDREX_SPEC",
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},
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{
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"ArchStdEvent": "STREX_PASS_SPEC",
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},
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{
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"ArchStdEvent": "STREX_FAIL_SPEC",
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},
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{
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"ArchStdEvent": "LD_SPEC",
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},
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{
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"ArchStdEvent": "ST_SPEC",
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},
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{
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"ArchStdEvent": "LDST_SPEC",
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},
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{
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"ArchStdEvent": "DP_SPEC",
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},
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{
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"ArchStdEvent": "ASE_SPEC",
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},
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{
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"ArchStdEvent": "VFP_SPEC",
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},
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{
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"ArchStdEvent": "PC_WRITE_SPEC",
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},
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{
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"ArchStdEvent": "CRYPTO_SPEC",
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},
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{
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"ArchStdEvent": "BR_IMMED_SPEC",
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},
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{
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"ArchStdEvent": "BR_RETURN_SPEC",
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC",
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},
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{
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"ArchStdEvent": "ISB_SPEC",
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},
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{
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"ArchStdEvent": "DSB_SPEC",
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},
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{
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"ArchStdEvent": "DMB_SPEC",
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},
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{
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"ArchStdEvent": "EXC_UNDEF",
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},
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{
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"ArchStdEvent": "EXC_SVC",
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},
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{
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"ArchStdEvent": "EXC_PABORT",
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},
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{
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"ArchStdEvent": "EXC_DABORT",
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},
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{
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"ArchStdEvent": "EXC_IRQ",
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},
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{
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"ArchStdEvent": "EXC_FIQ",
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},
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{
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"ArchStdEvent": "EXC_SMC",
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},
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{
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"ArchStdEvent": "EXC_HVC",
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},
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{
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"ArchStdEvent": "EXC_TRAP_PABORT",
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},
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{
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"ArchStdEvent": "EXC_TRAP_DABORT",
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},
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{
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"ArchStdEvent": "EXC_TRAP_OTHER",
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},
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{
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"ArchStdEvent": "EXC_TRAP_IRQ",
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},
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{
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"ArchStdEvent": "EXC_TRAP_FIQ",
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},
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{
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"ArchStdEvent": "RC_LD_SPEC",
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},
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{
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"ArchStdEvent": "RC_ST_SPEC",
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},
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]
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@ -14,6 +14,8 @@
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#Family-model,Version,Filename,EventType
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0x00000000410fd030,v1,arm/cortex-a53,core
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0x00000000420f1000,v1,arm/cortex-a53,core
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0x00000000410fd070,v1,arm/cortex-a57-a72,core
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0x00000000410fd080,v1,arm/cortex-a57-a72,core
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0x00000000420f5160,v1,cavium/thunderx2,core
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0x00000000430f0af0,v1,cavium/thunderx2,core
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0x00000000480fd010,v1,hisilicon/hip08,core
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