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serial: sh-sci: Improve interrupts description 

Describe interrupts property in more detail, especially when there are
more than one interrupt.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
Chris Brandt 2018-07-31 05:41:36 -05:00 committed by Greg Kroah-Hartman
parent 286d9b8c7d
commit 70a15ff0ed
1 changed files with 15 additions and 1 deletions
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16
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
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@ -73,7 +73,21 @@ Required properties:
family-specific and/or generic versions.
- reg: Base address and length of the I/O registers used by the UART.
- interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
- interrupts: Must contain one or more interrupt-specifiers for the SCIx.
If a single interrupt is expressed, then all events are
multiplexed into this single interrupt.
If multiple interrupts are provided by the hardware, the order
in which the interrupts are listed must match order below. Note
that some HW interrupt events may be muxed together resulting
in duplicate entries.
The interrupt order is as follows:
1. Error (ERI)
2. Receive buffer full (RXI)
3. Transmit buffer empty (TXI)
4. Break (BRI)
5. Data Ready (DRI)
6. Transmit End (TEI)
- clocks: Must contain a phandle and clock-specifier pair for each entry
in clock-names.