drm/i915/chv: Add DPLL state readout support
Add chv_crtc_clock_get() to read out the DPLL settings. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Fix compile due to bikeshedded headers in an earlier patch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6004,6 +6004,36 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
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}
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static void chv_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = pipe_config->cpu_transcoder;
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enum dpio_channel port = vlv_pipe_to_channel(pipe);
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intel_clock_t clock;
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u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
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int refclk = 100000;
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mutex_lock(&dev_priv->dpio_lock);
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cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
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pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
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pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
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pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
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mutex_unlock(&dev_priv->dpio_lock);
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clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
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clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
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clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
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clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
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clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
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chv_clock(refclk, &clock);
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/* clock.dot is the fast clock */
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pipe_config->port_clock = clock.dot / 5;
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}
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static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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@ -6073,7 +6103,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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DPLL_PORTB_READY_MASK);
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}
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if (IS_VALLEYVIEW(dev))
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if (IS_CHERRYVIEW(dev))
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chv_crtc_clock_get(crtc, pipe_config);
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else if (IS_VALLEYVIEW(dev))
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vlv_crtc_clock_get(crtc, pipe_config);
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else
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i9xx_crtc_clock_get(crtc, pipe_config);
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