drm/nouveau/pmu/fuc: replace mov+sethi with imm32

on gk208+ we can simply mov 32bits, so we should have a single mov there

v2: use or operator instead of add

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Karol Herbst 2016-03-02 17:23:05 +01:00 committed by Ben Skeggs
parent 4382e9091c
commit 70d97b5173
7 changed files with 3210 additions and 3218 deletions

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

View file

@ -98,8 +98,7 @@ host_send:
// $r0 - zero
host_recv:
// message from intr handler == HOST->PWR comms pending
mov $r1 (PROC_KERN & 0x0000ffff)
sethi $r1 (PROC_KERN & 0xffff0000)
imm32($r1, PROC_KERN)
cmp b32 $r14 $r1
bra e #host_send

View file

@ -51,8 +51,7 @@ time_next: .b32 0
// $r0 - zero
rd32:
nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
mov $r13 NV_PPWR_MMIO_CTRL_OP_RD
sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
imm32($r13, NV_PPWR_MMIO_CTRL_OP_RD | NV_PPWR_MMIO_CTRL_TRIGGER)
nv_iowr(NV_PPWR_MMIO_CTRL, $r13)
rd32_wait:
nv_iord($r13, NV_PPWR_MMIO_CTRL)
@ -70,9 +69,7 @@ rd32:
wr32:
nv_iowr(NV_PPWR_MMIO_ADDR, $r14)
nv_iowr(NV_PPWR_MMIO_DATA, $r13)
mov $r13 NV_PPWR_MMIO_CTRL_OP_WR
or $r13 NV_PPWR_MMIO_CTRL_MASK_B32_0
sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER
imm32($r13, NV_PPWR_MMIO_CTRL_OP_WR | NV_PPWR_MMIO_CTRL_MASK_B32_0 | NV_PPWR_MMIO_CTRL_TRIGGER)
#ifdef NVKM_FALCON_MMIO_TRAP
push $r13
@ -215,8 +212,7 @@ intr:
bra z #intr_subintr_skip_fifo
nv_iord($r12, NV_PPWR_FIFO_INTR)
push $r12
mov $r14 (PROC_HOST & 0x0000ffff)
sethi $r14 (PROC_HOST & 0xffff0000)
imm32($r14, PROC_HOST)
mov $r13 KMSG_FIFO
call(send)
pop $r12
@ -511,14 +507,12 @@ init:
#ifdef NVKM_FALCON_MMIO_UAS
// somehow allows the magic "access mmio via D[]" stuff that's
// used by the nv_rd32/nv_wr32 macros to work
mov $r1 0x0010
sethi $r1 NV_PPWR_UAS_CONFIG_ENABLE
imm32($r1, 0x10 | NV_PPWR_UAS_CONFIG_ENABLE)
nv_iowrs(NV_PPWR_UAS_CONFIG, $r1)
#endif
// route all interrupts except user0/1 and pause to fuc
mov $r1 0x00e0
sethi $r1 0x00000000
imm32($r1, 0xe0)
nv_iowr(NV_PPWR_INTR_ROUTE, $r1)
// enable watchdog and subintr intrs
@ -529,8 +523,8 @@ init:
nv_iowr(NV_PPWR_INTR_EN_SET, $r1)
// enable interrupts globally
mov $r1 #intr
sethi $r1 0x00000000
imm32($r1, #intr)
and $r1 0xffff
mov $iv0 $r1
bset $flags ie0

View file

@ -48,8 +48,7 @@ test_recv:
nv_iord($r1, NV_PPWR_DSCRATCH(2))
add b32 $r1 1
nv_iowr(NV_PPWR_DSCRATCH(2), $r1)
mov $r14 -0x2700 /* 0xd900, envyas grrr! */
sethi $r14 0x134f0000
imm32($r14, 0x134fd900)
call(timer)
ret