Merge branch 'brcm/stb-smp-uart' into next/drivers
This resolves a nonobvious merge conflict that I got wrong the first time. * brcm/stb-smp-uart: bus: brcmstb_gisb: save and restore GISB timeout bus: brcmstb_gisb: register the fault code hook ARM: brcmstb: Kconfig: drop unneeded symbol selections ARM: brcmstb: reintroduce SMP support ARM: brcmstb: add debug UART for earlyprintk support Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Florian Fainelli <f.fainelli@gmail.com>hifive-unleashed-5.1
Arnd Bergmann
commit
7135466151
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@ -139,6 +139,17 @@ choice
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Say Y here if you want kernel low-level debugging support
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on Marvell Berlin SoC based platforms.
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config DEBUG_BRCMSTB_UART
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bool "Use BRCMSTB UART for low-level debug"
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depends on ARCH_BRCMSTB
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select DEBUG_UART_8250
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help
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Say Y here if you want the debug print routines to direct
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their output to the first serial port on these devices.
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If you have a Broadcom STB chip and would like early print
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messages to appear over the UART, select this option.
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config DEBUG_CLPS711X_UART1
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bool "Kernel low-level debugging messages via UART1"
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depends on ARCH_CLPS711X
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@ -1153,6 +1164,7 @@ config DEBUG_UART_PHYS
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default 0xe0000000 if ARCH_SPEAR13XX
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default 0xe4007000 if DEBUG_HIP04_UART
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default 0xf0000be0 if ARCH_EBSA110
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default 0xf040ab00 if DEBUG_BRCMSTB_UART
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default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
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default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
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ARCH_ORION5X
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@ -1204,6 +1216,7 @@ config DEBUG_UART_VIRT
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default 0xfb002000 if DEBUG_CNS3XXX
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default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
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default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
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default 0xfc40ab00 if DEBUG_BRCMSTB_UART
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default 0xfcfe8600 if DEBUG_UART_BCM63XX
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default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
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default 0xfd000000 if ARCH_SPEAR13XX
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@ -1260,7 +1273,8 @@ config DEBUG_UART_8250_WORD
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ARCH_KEYSTONE || \
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DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
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DEBUG_DAVINCI_DA8XX_UART2 || \
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DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
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DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
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DEBUG_BRCMSTB_UART
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config DEBUG_UART_8250_FLOW_CONTROL
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bool "Enable flow control for 8250 UART"
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@ -118,10 +118,7 @@ config ARCH_BCM_63XX
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config ARCH_BRCMSTB
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bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
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depends on MMU
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select ARM_GIC
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select MIGHT_HAVE_PCI
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select HAVE_SMP
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select HAVE_ARM_ARCH_TIMER
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select BRCMSTB_GISB_ARB
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select BRCMSTB_L2_IRQ
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@ -38,5 +38,7 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
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ifeq ($(CONFIG_ARCH_BRCMSTB),y)
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CFLAGS_platsmp-brcmstb.o += -march=armv7-a
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obj-y += brcmstb.o
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obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
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endif
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@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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||||
* kind, whether express or implied; without even the implied warranty
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||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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*/
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#ifndef __BRCMSTB_H__
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#define __BRCMSTB_H__
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void brcmstb_secondary_startup(void);
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#endif /* __BRCMSTB_H__ */
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@ -0,0 +1,33 @@
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/*
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* SMP boot code for secondary CPUs
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* Based on arch/arm/mach-tegra/headsmp.S
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*
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* Copyright (C) 2010 NVIDIA, Inc.
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
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||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <asm/assembler.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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ENTRY(brcmstb_secondary_startup)
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/*
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* Ensure CPU is in a sane state by disabling all IRQs and switching
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* into SVC mode.
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*/
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(brcmstb_secondary_startup)
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@ -0,0 +1,329 @@
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/*
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* Broadcom STB CPU SMP and hotplug support for ARM
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*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
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||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/printk.h>
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#include <linux/regmap.h>
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#include <linux/smp.h>
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#include <linux/mfd/syscon.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/mach-types.h>
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#include <asm/smp_plat.h>
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#include "brcmstb.h"
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enum {
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ZONE_MAN_CLKEN_MASK = BIT(0),
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ZONE_MAN_RESET_CNTL_MASK = BIT(1),
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ZONE_MAN_MEM_PWR_MASK = BIT(4),
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ZONE_RESERVED_1_MASK = BIT(5),
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ZONE_MAN_ISO_CNTL_MASK = BIT(6),
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ZONE_MANUAL_CONTROL_MASK = BIT(7),
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ZONE_PWR_DN_REQ_MASK = BIT(9),
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ZONE_PWR_UP_REQ_MASK = BIT(10),
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ZONE_BLK_RST_ASSERT_MASK = BIT(12),
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ZONE_PWR_OFF_STATE_MASK = BIT(25),
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ZONE_PWR_ON_STATE_MASK = BIT(26),
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ZONE_DPG_PWR_STATE_MASK = BIT(28),
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ZONE_MEM_PWR_STATE_MASK = BIT(29),
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ZONE_RESET_STATE_MASK = BIT(31),
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CPU0_PWR_ZONE_CTRL_REG = 1,
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CPU_RESET_CONFIG_REG = 2,
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};
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static void __iomem *cpubiuctrl_block;
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static void __iomem *hif_cont_block;
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static u32 cpu0_pwr_zone_ctrl_reg;
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static u32 cpu_rst_cfg_reg;
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static u32 hif_cont_reg;
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* We must quiesce a dying CPU before it can be killed by the boot CPU. Because
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* one or more cache may be disabled, we must flush to ensure coherency. We
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* cannot use traditionl completion structures or spinlocks as they rely on
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* coherency.
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*/
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static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
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static int per_cpu_sw_state_rd(u32 cpu)
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{
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sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
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return per_cpu(per_cpu_sw_state, cpu);
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}
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static void per_cpu_sw_state_wr(u32 cpu, int val)
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{
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dmb();
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per_cpu(per_cpu_sw_state, cpu) = val;
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sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
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}
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#else
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static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
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#endif
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static void __iomem *pwr_ctrl_get_base(u32 cpu)
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{
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void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
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base += (cpu_logical_map(cpu) * 4);
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return base;
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}
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static u32 pwr_ctrl_rd(u32 cpu)
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{
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void __iomem *base = pwr_ctrl_get_base(cpu);
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return readl_relaxed(base);
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}
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static void pwr_ctrl_wr(u32 cpu, u32 val)
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{
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void __iomem *base = pwr_ctrl_get_base(cpu);
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writel(val, base);
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}
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static void cpu_rst_cfg_set(u32 cpu, int set)
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{
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u32 val;
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val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
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if (set)
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val |= BIT(cpu_logical_map(cpu));
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else
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val &= ~BIT(cpu_logical_map(cpu));
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writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
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}
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static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
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{
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const int reg_ofs = cpu_logical_map(cpu) * 8;
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writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
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writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
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}
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static void brcmstb_cpu_boot(u32 cpu)
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{
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/* Mark this CPU as "up" */
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per_cpu_sw_state_wr(cpu, 1);
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/*
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* Set the reset vector to point to the secondary_startup
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* routine
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*/
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cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
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/* Unhalt the cpu */
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cpu_rst_cfg_set(cpu, 0);
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}
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|
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static void brcmstb_cpu_power_on(u32 cpu)
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{
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/*
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* The secondary cores power was cut, so we must go through
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* power-on initialization.
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||||
*/
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u32 tmp;
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/* Request zone power up */
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pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
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|
||||
/* Wait for the power up FSM to complete */
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do {
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tmp = pwr_ctrl_rd(cpu);
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} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
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||||
}
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||||
|
||||
static int brcmstb_cpu_get_power_state(u32 cpu)
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||||
{
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||||
int tmp = pwr_ctrl_rd(cpu);
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||||
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
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}
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||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
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||||
|
||||
static void brcmstb_cpu_die(u32 cpu)
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||||
{
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||||
v7_exit_coherency_flush(all);
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||||
|
||||
per_cpu_sw_state_wr(cpu, 0);
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||||
|
||||
/* Sit and wait to die */
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||||
wfi();
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||||
|
||||
/* We should never get here... */
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||||
while (1)
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||||
;
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||||
}
|
||||
|
||||
static int brcmstb_cpu_kill(u32 cpu)
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||||
{
|
||||
u32 tmp;
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||||
|
||||
while (per_cpu_sw_state_rd(cpu))
|
||||
;
|
||||
|
||||
/* Program zone reset */
|
||||
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
|
||||
ZONE_PWR_DN_REQ_MASK);
|
||||
|
||||
/* Verify zone reset */
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
if (!(tmp & ZONE_RESET_STATE_MASK))
|
||||
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
|
||||
__func__, cpu);
|
||||
|
||||
/* Wait for power down */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
|
||||
|
||||
/* Flush pipeline before resetting CPU */
|
||||
mb();
|
||||
|
||||
/* Assert reset on the CPU */
|
||||
cpu_rst_cfg_set(cpu, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cpu";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cpubiuctrl_block = of_iomap(syscon_np, 0);
|
||||
if (!cpubiuctrl_block) {
|
||||
pr_err("iomap failed for cpubiuctrl_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
|
||||
&cpu0_pwr_zone_ctrl_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 1st entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
|
||||
&cpu_rst_cfg_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
of_node_put(syscon_np);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init setup_hifcont_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cont";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
hif_cont_block = of_iomap(syscon_np, 0);
|
||||
if (!hif_cont_block) {
|
||||
pr_err("iomap failed for hif_cont_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* Offset is at top of hif_cont_block */
|
||||
hif_cont_reg = 0;
|
||||
|
||||
cleanup:
|
||||
of_node_put(syscon_np);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
|
||||
{
|
||||
int rc;
|
||||
struct device_node *np;
|
||||
char *name;
|
||||
|
||||
name = "brcm,brcmstb-smpboot";
|
||||
np = of_find_compatible_node(NULL, NULL, name);
|
||||
if (!np) {
|
||||
pr_err("can't find compatible node %s\n", name);
|
||||
return;
|
||||
}
|
||||
|
||||
rc = setup_hifcpubiuctrl_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
rc = setup_hifcont_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
}
|
||||
|
||||
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
/* Missing the brcm,brcmstb-smpboot DT node? */
|
||||
if (!cpubiuctrl_block || !hif_cont_block)
|
||||
return -ENODEV;
|
||||
|
||||
/* Bring up power to the core if necessary */
|
||||
if (brcmstb_cpu_get_power_state(cpu) == 0)
|
||||
brcmstb_cpu_power_on(cpu);
|
||||
|
||||
brcmstb_cpu_boot(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct smp_operations brcmstb_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
|
||||
.smp_boot_secondary = brcmstb_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = brcmstb_cpu_kill,
|
||||
.cpu_die = brcmstb_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/list.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
#include <asm/bug.h>
|
||||
|
|
@ -94,6 +95,7 @@ struct brcmstb_gisb_arb_device {
|
|||
struct list_head next;
|
||||
u32 valid_mask;
|
||||
const char *master_names[sizeof(u32) * BITS_PER_BYTE];
|
||||
u32 saved_timeout;
|
||||
};
|
||||
|
||||
static LIST_HEAD(brcmstb_gisb_arb_device_list);
|
||||
|
|
@ -226,12 +228,6 @@ static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
|
|||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void __init brcmstb_hook_fault_code(void)
|
||||
{
|
||||
hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
}
|
||||
#endif
|
||||
|
||||
static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
|
||||
|
|
@ -346,17 +342,56 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
|
|||
|
||||
list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
#endif
|
||||
|
||||
dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
|
||||
gdev->base, timeout_irq, tea_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int brcmstb_gisb_arb_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
|
||||
|
||||
gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Make sure we provide the same timeout value that was configured before, and
|
||||
* do this before the GISB timeout interrupt handler has any chance to run.
|
||||
*/
|
||||
static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
|
||||
|
||||
gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define brcmstb_gisb_arb_suspend NULL
|
||||
#define brcmstb_gisb_arb_resume_noirq NULL
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
|
||||
.suspend = brcmstb_gisb_arb_suspend,
|
||||
.resume_noirq = brcmstb_gisb_arb_resume_noirq,
|
||||
};
|
||||
|
||||
static struct platform_driver brcmstb_gisb_arb_driver = {
|
||||
.driver = {
|
||||
.name = "brcm-gisb-arb",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = brcmstb_gisb_arb_of_match,
|
||||
.pm = &brcmstb_gisb_arb_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue