drm/i915/gvt: Add software PTE flag to mark special 64K splited entry
This add a software PTE flag on the Ignored bit of PTE. It will be used to identify splited 64K shadow entries. v2: fix mask definition. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -348,6 +348,9 @@ static inline int gtt_set_entry64(void *pt,
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#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
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#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
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#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
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#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
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static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
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{
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unsigned long pfn;
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@ -427,6 +430,21 @@ static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
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e->val64 |= _PAGE_PRESENT;
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}
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static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
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{
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return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
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}
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static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
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{
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e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
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}
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static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
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{
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e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
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}
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/*
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* Per-platform GMA routines.
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*/
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@ -461,6 +479,9 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
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.test_pse = gen8_gtt_test_pse,
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.clear_ips = gen8_gtt_clear_ips,
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.test_ips = gen8_gtt_test_ips,
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.clear_64k_splited = gen8_gtt_clear_64k_splited,
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.set_64k_splited = gen8_gtt_set_64k_splited,
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.test_64k_splited = gen8_gtt_test_64k_splited,
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.get_pfn = gen8_gtt_get_pfn,
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.set_pfn = gen8_gtt_set_pfn,
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};
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@ -65,6 +65,9 @@ struct intel_gvt_gtt_pte_ops {
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bool (*test_pse)(struct intel_gvt_gtt_entry *e);
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bool (*test_ips)(struct intel_gvt_gtt_entry *e);
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void (*clear_ips)(struct intel_gvt_gtt_entry *e);
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bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
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void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
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unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
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};
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