net/mlx5: CmdIF, Use async events chain
Remove the explicit call to mlx5_cmd_comp_handler on MLX5_EVENT_TYPE_CMD and let command interface to register its own handler when its ready. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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0cf53c1247
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@ -40,9 +40,11 @@
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#include <linux/random.h>
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#include <linux/io-mapping.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/eq.h>
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#include <linux/debugfs.h>
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#include "mlx5_core.h"
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#include "lib/eq.h"
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enum {
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CMD_IF_REV = 5,
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@ -805,6 +807,8 @@ static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
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return MLX5_GET(mbox_in, in->first.data, opcode);
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}
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static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
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static void cb_timeout_handler(struct work_struct *work)
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{
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struct delayed_work *dwork = container_of(work, struct delayed_work,
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@ -1412,14 +1416,32 @@ static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
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up(&cmd->sem);
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}
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static int cmd_comp_notifier(struct notifier_block *nb,
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unsigned long type, void *data)
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{
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struct mlx5_core_dev *dev;
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struct mlx5_cmd *cmd;
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struct mlx5_eqe *eqe;
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cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
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dev = container_of(cmd, struct mlx5_core_dev, cmd);
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eqe = data;
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mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
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return NOTIFY_OK;
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}
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void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
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{
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MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
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mlx5_eq_notifier_register(dev, &dev->cmd.nb);
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mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
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}
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void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
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{
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mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
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mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
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}
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static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
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@ -1435,7 +1457,7 @@ static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
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}
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}
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
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static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
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{
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struct mlx5_cmd *cmd = &dev->cmd;
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struct mlx5_cmd_work_ent *ent;
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@ -1533,7 +1555,29 @@ void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
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}
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}
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}
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EXPORT_SYMBOL(mlx5_cmd_comp_handler);
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void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
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{
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unsigned long flags;
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u64 vector;
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/* wait for pending handlers to complete */
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mlx5_eq_synchronize_cmd_irq(dev);
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spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
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vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
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if (!vector)
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goto no_trig;
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vector |= MLX5_TRIGGERED_CMD_COMP;
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
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mlx5_cmd_comp_handler(dev, vector, true);
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return;
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no_trig:
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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}
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static int status_to_err(u8 status)
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{
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@ -368,10 +368,6 @@ static irqreturn_t mlx5_eq_async_int(int irq, void *eq_ptr)
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mlx5_srq_event(dev, rsn, eqe->type);
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break;
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case MLX5_EVENT_TYPE_CMD:
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mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
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break;
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case MLX5_EVENT_TYPE_PORT_CHANGE:
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port = (eqe->data.port.port >> 4) & 0xf;
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switch (eqe->sub_type) {
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@ -79,29 +79,6 @@ void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state)
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&dev->iseg->cmdq_addr_l_sz);
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}
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static void trigger_cmd_completions(struct mlx5_core_dev *dev)
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{
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unsigned long flags;
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u64 vector;
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/* wait for pending handlers to complete */
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mlx5_eq_synchronize_cmd_irq(dev);
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spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
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vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
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if (!vector)
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goto no_trig;
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vector |= MLX5_TRIGGERED_CMD_COMP;
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
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mlx5_cmd_comp_handler(dev, vector, true);
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return;
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no_trig:
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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}
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static int in_fatal(struct mlx5_core_dev *dev)
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{
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struct mlx5_core_health *health = &dev->priv.health;
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@ -125,7 +102,7 @@ void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
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mlx5_core_err(dev, "start\n");
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if (pci_channel_offline(dev->pdev) || in_fatal(dev) || force) {
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dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
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trigger_cmd_completions(dev);
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mlx5_cmd_trigger_completions(dev);
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}
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mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 1);
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@ -127,7 +127,7 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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int mlx5_wait_for_vf_pages(struct mlx5_core_dev *dev);
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u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev);
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void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
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void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
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int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
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void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
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@ -278,6 +278,8 @@ struct mlx5_cmd_stats {
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};
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struct mlx5_cmd {
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struct mlx5_nb nb;
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void *cmd_alloc_buf;
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dma_addr_t alloc_dma;
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int alloc_size;
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