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cxgb4/cxgb4vf: Updated the LSO transfer length in CPL_TX_PKT_LSO for T5 

Update the lso length for T5 adapter and fix PIDX_T5 macro

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Hariprasad Shenai 2014-10-09 05:48:45 +05:30 committed by David S. Miller
parent ea97caeee2
commit 7207c0d154
4 changed files with 11 additions and 5 deletions
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5
drivers/net/ethernet/chelsio/cxgb4/sge.c
View File

@ -1123,7 +1123,10 @@ out_free: dev_kfree_skb_any(skb);
lso->c.ipid_ofst = htons(0);
lso->c.mss = htons(ssi->gso_size);
lso->c.seqno_offset = htonl(0);
lso->c.len = htonl(skb->len);
if (is_t4(adap->params.chip))
lso->c.len = htonl(skb->len);
else
lso->c.len = htonl(LSO_T5_XFER_SIZE(skb->len));
cpl = (void *)(lso + 1);
cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
TXPKT_IPHDR_LEN(l3hdr_len) |

1
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
View File

@ -527,6 +527,7 @@ struct cpl_tx_pkt_lso_core {
#define LSO_LAST_SLICE (1 << 22)
#define LSO_FIRST_SLICE (1 << 23)
#define LSO_OPCODE(x) ((x) << 24)
#define LSO_T5_XFER_SIZE(x) ((x) << 0)
__be16 ipid_ofst;
__be16 mss;
__be32 seqno_offset;

5
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -72,9 +72,8 @@
#define PIDX_MASK 0x00003fffU
#define PIDX_SHIFT 0
#define PIDX(x) ((x) << PIDX_SHIFT)
#define S_PIDX_T5 0
#define M_PIDX_T5 0x1fffU
#define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
#define PIDX_SHIFT_T5 0
#define PIDX_T5(x) ((x) << PIDX_SHIFT_T5)
#define SGE_TIMERREGS 6

5
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
View File

@ -1208,7 +1208,10 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
lso->ipid_ofst = cpu_to_be16(0);
lso->mss = cpu_to_be16(ssi->gso_size);
lso->seqno_offset = cpu_to_be32(0);
lso->len = cpu_to_be32(skb->len);
if (is_t4(adapter->params.chip))
lso->len = cpu_to_be32(skb->len);
else
lso->len = cpu_to_be32(LSO_T5_XFER_SIZE(skb->len));
/*
* Set up TX Packet CPL pointer, control word and perform