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MLK-23694-1 clk: imx8mp: add 2079MHz rate for video pll1 

On i.MX8MP platform, 'media_disp1_pix', 'media_disp2_pix',
'media_mipi_phy1_ref' and 'media_ldb' clocks share same
video PLL 'video_pll1'. And since 'media_disp2_pix' needs
video PLL rate to be 1039.5MHz and 'media_mipi_phy1_ref'
rate is usually set to be 27MHz. So add 2079MHz rate for
'video_pll1' to support all of these requirements.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Fancy Fang 2020-03-16 08:18:10 +08:00
parent 919a85dbb1
commit 722638573e
1 changed files with 1 additions and 0 deletions
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drivers/clk/imx/clk-imx8mp.c
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@ -54,6 +54,7 @@ static const struct imx_pll14xx_rate_table imx8mp_audiopll_tbl[] = {
};
static const struct imx_pll14xx_rate_table imx8mp_videopll_tbl[] = {
PLL_1443X_RATE(2079000000U, 173, 1, 1, 16384),
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),