pinctrl: sh-pfc: Updates for v4.16
- Add CAN pin groups on RZ/G1E, - Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3, - Add support for the new R-Car V3M SoC, - Add support for I2C on R-Car D3, - Small fixes and cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaM5QbAAoJEEgEtLw/Ve77DL0QAK5qKY/9Jt9PASqIvEJMsc5U Ns8ULXaynLSvOLHWNCFN0MD53gnKsQVOFMynsf1NWJ5j2fqCCu5nkrxoZKTTxMWs 1TJGXBrCqQLzQspUXxdjFwJHIOeXCDQllw5Xsdq4MbzmlDRr+G9jj7CxLK5pjk1B jUZ+cfDBwuSWlDymrwcEAREBQtg7HYBlkt1zyFXPJYu5R/iGdE1ih39yBqTPka1/ ua+d2FdGOUeOXoqqAkkJZ9+8YsITAoU+YoriKgf2I/vLiovBCBSdfenJZ5He+Hth 7EWaIiK1Y/zdwadUtzC6/FGckkn4kj6+t5koLrXaSXce/TO4uWN6iIAiWATd26CY sxv1+likNAN5rGXtowXiyyOo26bZ/nFchgT4JC8FZdG0DeseOAFYE8pn8TKvDdSZ RTPmo6r/CiFsyn3oAzOjSMbafEvXJBZX/QQDgsS1orboWAbi8YtswacIPc/GGBhr iCc28erUks2fSq4+3W64Q+s/061I7NiES13ry9o3srfjWb45PEdjO+FUMN8chazt sNrWWrRB6HEs9N5/jGA6ZRPnbZnJnl8d1sxY/Tpj32To0kDWn3CVlGwLZDDaRIJf Zs/q8i/2D97RyiXtTtKacO2fZpHWQl+9kDKXOEjVcLZh5utkKM+L2cBSHoG5cCRn XsPp6HLHI4BdJnap4+La =dwjl -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.16 - Add CAN pin groups on RZ/G1E, - Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3, - Add support for the new R-Car V3M SoC, - Add support for I2C on R-Car D3, - Small fixes and cleanups.
This commit is contained in:
Linus Walleij
commit
723dd2f0de
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@ -24,6 +24,7 @@ Required Properties:
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- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
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- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
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- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
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- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
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- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
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- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
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@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
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depends on ARCH_R8A7796
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A77970
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def_bool y
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depends on ARCH_R8A77970
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A77995
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def_bool y
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depends on ARCH_R8A77995
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@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
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obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
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obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
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@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a7796_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77970
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{
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.compatible = "renesas,pfc-r8a77970",
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.data = &r8a77970_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A77995
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{
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.compatible = "renesas,pfc-r8a77995",
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@ -4826,6 +4826,10 @@ static const char * const can0_groups[] = {
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"can0_data_d",
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"can0_data_e",
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"can0_data_f",
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/*
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* Retained for backwards compatibility, use can_clk_groups in new
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* designs.
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*/
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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@ -4837,6 +4841,21 @@ static const char * const can1_groups[] = {
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"can1_data_b",
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"can1_data_c",
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"can1_data_d",
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/*
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* Retained for backwards compatibility, use can_clk_groups in new
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* designs.
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*/
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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"can_clk_d",
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};
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/*
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* can_clk_groups allows for independent configuration, use can_clk function
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* in new designs.
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*/
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static const char * const can_clk_groups[] = {
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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@ -5308,7 +5327,7 @@ static const char * const vin2_groups[] = {
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};
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static const struct {
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struct sh_pfc_function common[56];
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struct sh_pfc_function common[57];
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struct sh_pfc_function r8a779x[2];
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} pinmux_functions = {
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.common = {
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@ -5316,6 +5335,7 @@ static const struct {
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SH_PFC_FUNCTION(avb),
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SH_PFC_FUNCTION(can0),
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SH_PFC_FUNCTION(can1),
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SH_PFC_FUNCTION(can_clk),
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SH_PFC_FUNCTION(du),
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SH_PFC_FUNCTION(du0),
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SH_PFC_FUNCTION(du1),
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@ -1608,6 +1608,116 @@ static const unsigned int avb_gmii_mux[] = {
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AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
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AVB_COL_MARK,
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};
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/* - CAN -------------------------------------------------------------------- */
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static const unsigned int can0_data_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
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};
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static const unsigned int can0_data_mux[] = {
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CAN0_TX_MARK, CAN0_RX_MARK,
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};
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static const unsigned int can0_data_b_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
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};
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static const unsigned int can0_data_b_mux[] = {
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CAN0_TX_B_MARK, CAN0_RX_B_MARK,
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};
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static const unsigned int can0_data_c_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
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};
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static const unsigned int can0_data_c_mux[] = {
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CAN0_TX_C_MARK, CAN0_RX_C_MARK,
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};
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static const unsigned int can0_data_d_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
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};
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static const unsigned int can0_data_d_mux[] = {
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CAN0_TX_D_MARK, CAN0_RX_D_MARK,
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};
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static const unsigned int can1_data_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
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};
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static const unsigned int can1_data_mux[] = {
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CAN1_TX_MARK, CAN1_RX_MARK,
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};
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static const unsigned int can1_data_b_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
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};
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static const unsigned int can1_data_b_mux[] = {
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CAN1_TX_B_MARK, CAN1_RX_B_MARK,
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};
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static const unsigned int can1_data_c_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
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};
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static const unsigned int can1_data_c_mux[] = {
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CAN1_TX_C_MARK, CAN1_RX_C_MARK,
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};
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static const unsigned int can1_data_d_pins[] = {
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/* TX, RX */
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RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
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};
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static const unsigned int can1_data_d_mux[] = {
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CAN1_TX_D_MARK, CAN1_RX_D_MARK,
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};
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static const unsigned int can_clk_pins[] = {
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/* CLK */
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RCAR_GP_PIN(3, 31),
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};
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static const unsigned int can_clk_mux[] = {
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CAN_CLK_MARK,
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};
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static const unsigned int can_clk_b_pins[] = {
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/* CLK */
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RCAR_GP_PIN(1, 23),
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};
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static const unsigned int can_clk_b_mux[] = {
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CAN_CLK_B_MARK,
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};
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static const unsigned int can_clk_c_pins[] = {
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/* CLK */
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RCAR_GP_PIN(1, 0),
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};
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static const unsigned int can_clk_c_mux[] = {
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CAN_CLK_C_MARK,
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};
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static const unsigned int can_clk_d_pins[] = {
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/* CLK */
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RCAR_GP_PIN(5, 0),
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};
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static const unsigned int can_clk_d_mux[] = {
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CAN_CLK_D_MARK,
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};
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/* - DU --------------------------------------------------------------------- */
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static const unsigned int du0_rgb666_pins[] = {
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/* R[7:2], G[7:2], B[7:2] */
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@ -3459,6 +3569,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(avb_mdio),
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SH_PFC_PIN_GROUP(avb_mii),
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SH_PFC_PIN_GROUP(avb_gmii),
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SH_PFC_PIN_GROUP(can0_data),
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SH_PFC_PIN_GROUP(can0_data_b),
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SH_PFC_PIN_GROUP(can0_data_c),
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SH_PFC_PIN_GROUP(can0_data_d),
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SH_PFC_PIN_GROUP(can1_data),
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SH_PFC_PIN_GROUP(can1_data_b),
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SH_PFC_PIN_GROUP(can1_data_c),
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SH_PFC_PIN_GROUP(can1_data_d),
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SH_PFC_PIN_GROUP(can_clk),
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SH_PFC_PIN_GROUP(can_clk_b),
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SH_PFC_PIN_GROUP(can_clk_c),
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SH_PFC_PIN_GROUP(can_clk_d),
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SH_PFC_PIN_GROUP(du0_rgb666),
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SH_PFC_PIN_GROUP(du0_rgb888),
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SH_PFC_PIN_GROUP(du0_clk0_out),
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@ -3731,6 +3853,47 @@ static const char * const avb_groups[] = {
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"avb_gmii",
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};
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static const char * const can0_groups[] = {
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"can0_data",
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"can0_data_b",
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"can0_data_c",
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"can0_data_d",
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/*
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* Retained for backwards compatibility, use can_clk_groups in new
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* designs.
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*/
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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"can_clk_d",
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};
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static const char * const can1_groups[] = {
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"can1_data",
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"can1_data_b",
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"can1_data_c",
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"can1_data_d",
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/*
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* Retained for backwards compatibility, use can_clk_groups in new
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* designs.
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*/
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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"can_clk_d",
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};
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/*
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* can_clk_groups allows for independent configuration, use can_clk function
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* in new designs.
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*/
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static const char * const can_clk_groups[] = {
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"can_clk",
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"can_clk_b",
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"can_clk_c",
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"can_clk_d",
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};
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static const char * const du0_groups[] = {
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"du0_rgb666",
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"du0_rgb888",
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@ -4102,6 +4265,9 @@ static const char * const vin1_groups[] = {
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(audio_clk),
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SH_PFC_FUNCTION(avb),
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SH_PFC_FUNCTION(can0),
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SH_PFC_FUNCTION(can1),
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SH_PFC_FUNCTION(can_clk),
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SH_PFC_FUNCTION(du0),
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SH_PFC_FUNCTION(du1),
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SH_PFC_FUNCTION(eth),
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@ -1397,7 +1397,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
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PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
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PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
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PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
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PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
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PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
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PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
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PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
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@ -20,7 +20,7 @@
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
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@ -55,6 +55,7 @@
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#define GPSR0_0 F_(D0, IP5_15_12)
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/* GPSR1 */
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#define GPSR1_28 FM(CLKOUT)
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#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
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#define GPSR1_26 F_(WE1_N, IP5_7_4)
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#define GPSR1_25 F_(WE0_N, IP5_3_0)
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@ -157,11 +158,11 @@
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#define GPSR5_11 F_(RX2_A, IP13_7_4)
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#define GPSR5_10 F_(TX2_A, IP13_3_0)
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#define GPSR5_9 F_(SCK2, IP12_31_28)
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#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
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#define GPSR5_8 F_(RTS1_N, IP12_27_24)
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#define GPSR5_7 F_(CTS1_N, IP12_23_20)
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#define GPSR5_6 F_(TX1_A, IP12_19_16)
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#define GPSR5_5 F_(RX1_A, IP12_15_12)
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#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
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#define GPSR5_4 F_(RTS0_N, IP12_11_8)
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#define GPSR5_3 F_(CTS0_N, IP12_7_4)
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#define GPSR5_2 F_(TX0, IP12_3_0)
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#define GPSR5_1 F_(RX0, IP11_31_28)
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@ -214,16 +215,16 @@
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#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -236,7 +237,7 @@
|
|||
#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -252,7 +253,7 @@
|
|||
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -265,7 +266,7 @@
|
|||
#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -312,11 +313,11 @@
|
|||
#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -368,7 +369,7 @@
|
|||
GPSR6_31 \
|
||||
GPSR6_30 \
|
||||
GPSR6_29 \
|
||||
GPSR6_28 \
|
||||
GPSR1_28 GPSR6_28 \
|
||||
GPSR1_27 GPSR6_27 \
|
||||
GPSR1_26 GPSR6_26 \
|
||||
GPSR1_25 GPSR5_25 GPSR6_25 \
|
||||
|
|
@ -548,7 +549,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
|
|||
FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
|
||||
FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
|
||||
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
|
||||
FM(CLKOUT) FM(PRESETOUT) \
|
||||
FM(PRESETOUT) \
|
||||
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
|
||||
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
|
||||
|
||||
|
|
@ -587,6 +588,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_SINGLE(AVS1),
|
||||
PINMUX_SINGLE(AVS2),
|
||||
PINMUX_SINGLE(CLKOUT),
|
||||
PINMUX_SINGLE(HDMI0_CEC),
|
||||
PINMUX_SINGLE(HDMI1_CEC),
|
||||
PINMUX_SINGLE(I2C_SEL_0_1),
|
||||
|
|
@ -622,7 +624,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
|
||||
|
|
@ -650,7 +652,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, A25),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
|
||||
PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
|
||||
|
|
@ -658,7 +659,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, A24),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
|
||||
PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
|
||||
|
|
@ -666,7 +666,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, A23),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
|
||||
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
|
||||
|
|
@ -675,18 +674,15 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, A22),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
|
||||
PINMUX_IPSR_GPSR(IP1_23_20, A21),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
|
||||
PINMUX_IPSR_GPSR(IP1_27_24, A20),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
|
||||
|
||||
|
|
@ -766,7 +762,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP3_7_4, A10),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP3_11_8, A11),
|
||||
|
|
@ -869,7 +865,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
|
||||
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
|
||||
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
|
||||
|
|
@ -950,7 +946,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP6_31_28, D12),
|
||||
|
|
@ -1159,7 +1155,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
|
||||
PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
|
||||
|
|
@ -1188,7 +1184,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
|
||||
PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
|
||||
|
|
@ -1781,6 +1777,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
|
|||
AVB_AVTP_CAPTURE_B_MARK,
|
||||
};
|
||||
|
||||
/* - CAN ------------------------------------------------------------------ */
|
||||
static const unsigned int can0_data_a_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
|
||||
};
|
||||
static const unsigned int can0_data_a_mux[] = {
|
||||
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
|
||||
};
|
||||
static const unsigned int can0_data_b_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
static const unsigned int can0_data_b_mux[] = {
|
||||
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
|
||||
};
|
||||
static const unsigned int can1_data_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
|
||||
};
|
||||
static const unsigned int can1_data_mux[] = {
|
||||
CAN1_TX_MARK, CAN1_RX_MARK,
|
||||
};
|
||||
|
||||
/* - CAN Clock -------------------------------------------------------------- */
|
||||
static const unsigned int can_clk_pins[] = {
|
||||
/* CLK */
|
||||
RCAR_GP_PIN(1, 25),
|
||||
};
|
||||
static const unsigned int can_clk_mux[] = {
|
||||
CAN_CLK_MARK,
|
||||
};
|
||||
|
||||
/* - CAN FD --------------------------------------------------------------- */
|
||||
static const unsigned int canfd0_data_a_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
|
||||
};
|
||||
static const unsigned int canfd0_data_a_mux[] = {
|
||||
CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
|
||||
};
|
||||
static const unsigned int canfd0_data_b_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
static const unsigned int canfd0_data_b_mux[] = {
|
||||
CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
|
||||
};
|
||||
static const unsigned int canfd1_data_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
|
||||
};
|
||||
static const unsigned int canfd1_data_mux[] = {
|
||||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
/* - DRIF0 --------------------------------------------------------------- */
|
||||
static const unsigned int drif0_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
|
|
@ -3196,7 +3247,7 @@ static const unsigned int scif0_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
|
||||
};
|
||||
static const unsigned int scif0_ctrl_mux[] = {
|
||||
RTS0_N_TANS_MARK, CTS0_N_MARK,
|
||||
RTS0_N_MARK, CTS0_N_MARK,
|
||||
};
|
||||
/* - SCIF1 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif1_data_a_pins[] = {
|
||||
|
|
@ -3218,7 +3269,7 @@ static const unsigned int scif1_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
|
||||
};
|
||||
static const unsigned int scif1_ctrl_mux[] = {
|
||||
RTS1_N_TANS_MARK, CTS1_N_MARK,
|
||||
RTS1_N_MARK, CTS1_N_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int scif1_data_b_pins[] = {
|
||||
|
|
@ -3270,7 +3321,7 @@ static const unsigned int scif3_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
|
||||
};
|
||||
static const unsigned int scif3_ctrl_mux[] = {
|
||||
RTS3_N_TANS_MARK, CTS3_N_MARK,
|
||||
RTS3_N_MARK, CTS3_N_MARK,
|
||||
};
|
||||
static const unsigned int scif3_data_b_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3299,7 +3350,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
|
|||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_a_mux[] = {
|
||||
RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
|
||||
RTS4_N_A_MARK, CTS4_N_A_MARK,
|
||||
};
|
||||
static const unsigned int scif4_data_b_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3320,7 +3371,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
|
|||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_b_mux[] = {
|
||||
RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
|
||||
RTS4_N_B_MARK, CTS4_N_B_MARK,
|
||||
};
|
||||
static const unsigned int scif4_data_c_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3341,7 +3392,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
|
|||
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_c_mux[] = {
|
||||
RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
|
||||
RTS4_N_C_MARK, CTS4_N_C_MARK,
|
||||
};
|
||||
/* - SCIF5 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif5_data_a_pins[] = {
|
||||
|
|
@ -3843,6 +3894,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match_b),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
|
||||
SH_PFC_PIN_GROUP(can0_data_a),
|
||||
SH_PFC_PIN_GROUP(can0_data_b),
|
||||
SH_PFC_PIN_GROUP(can1_data),
|
||||
SH_PFC_PIN_GROUP(can_clk),
|
||||
SH_PFC_PIN_GROUP(canfd0_data_a),
|
||||
SH_PFC_PIN_GROUP(canfd0_data_b),
|
||||
SH_PFC_PIN_GROUP(canfd1_data),
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data1_a),
|
||||
|
|
@ -4154,6 +4212,28 @@ static const char * const avb_groups[] = {
|
|||
"avb_avtp_capture_b",
|
||||
};
|
||||
|
||||
static const char * const can0_groups[] = {
|
||||
"can0_data_a",
|
||||
"can0_data_b",
|
||||
};
|
||||
|
||||
static const char * const can1_groups[] = {
|
||||
"can1_data",
|
||||
};
|
||||
|
||||
static const char * const can_clk_groups[] = {
|
||||
"can_clk",
|
||||
};
|
||||
|
||||
static const char * const canfd0_groups[] = {
|
||||
"canfd0_data_a",
|
||||
"canfd0_data_b",
|
||||
};
|
||||
|
||||
static const char * const canfd1_groups[] = {
|
||||
"canfd1_data",
|
||||
};
|
||||
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
|
|
@ -4559,6 +4639,11 @@ static const char * const usb30_groups[] = {
|
|||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb),
|
||||
SH_PFC_FUNCTION(can0),
|
||||
SH_PFC_FUNCTION(can1),
|
||||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(canfd0),
|
||||
SH_PFC_FUNCTION(canfd1),
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
|
|
@ -4644,7 +4729,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
GP_1_28_FN, GPSR1_28,
|
||||
GP_1_27_FN, GPSR1_27,
|
||||
GP_1_26_FN, GPSR1_26,
|
||||
GP_1_25_FN, GPSR1_25,
|
||||
|
|
@ -5246,7 +5331,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
|
||||
{ PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
|
||||
{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
|
||||
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
|
||||
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
|
||||
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
|
||||
|
|
@ -5342,11 +5427,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
|
||||
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
|
||||
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
|
||||
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
|
||||
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
|
||||
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
|
||||
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
|
||||
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
|
||||
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
|
||||
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
|
||||
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
|
||||
|
|
@ -5507,7 +5592,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[31] = RCAR_GP_PIN(1, 19), /* A19 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
|
||||
[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
|
||||
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
|
||||
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
|
||||
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
|
||||
|
|
@ -5591,11 +5676,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
|
||||
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
|
||||
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
|
||||
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
|
||||
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
|
||||
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
|
||||
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
|
||||
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
|
||||
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
|
||||
|
|
|
|||
|
|
@ -163,11 +163,11 @@
|
|||
#define GPSR5_11 F_(RX2_A, IP13_7_4)
|
||||
#define GPSR5_10 F_(TX2_A, IP13_3_0)
|
||||
#define GPSR5_9 F_(SCK2, IP12_31_28)
|
||||
#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
|
||||
#define GPSR5_8 F_(RTS1_N, IP12_27_24)
|
||||
#define GPSR5_7 F_(CTS1_N, IP12_23_20)
|
||||
#define GPSR5_6 F_(TX1_A, IP12_19_16)
|
||||
#define GPSR5_5 F_(RX1_A, IP12_15_12)
|
||||
#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
|
||||
#define GPSR5_4 F_(RTS0_N, IP12_11_8)
|
||||
#define GPSR5_3 F_(CTS0_N, IP12_7_4)
|
||||
#define GPSR5_2 F_(TX0, IP12_3_0)
|
||||
#define GPSR5_1 F_(RX0, IP11_31_28)
|
||||
|
|
@ -220,16 +220,16 @@
|
|||
#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -240,7 +240,7 @@
|
|||
#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
|
||||
|
|
@ -258,7 +258,7 @@
|
|||
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -271,7 +271,7 @@
|
|||
#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
|
||||
|
|
@ -318,11 +318,11 @@
|
|||
#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -626,7 +626,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
|
||||
|
|
@ -654,7 +654,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, A25),
|
||||
PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
|
||||
PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
|
||||
|
|
@ -662,7 +661,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, A24),
|
||||
PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
|
||||
PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
|
||||
|
|
@ -670,7 +668,6 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, A23),
|
||||
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
|
||||
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
|
||||
|
|
@ -678,18 +675,15 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
|
||||
PINMUX_IPSR_GPSR(IP1_19_16, A22),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
|
||||
PINMUX_IPSR_GPSR(IP1_23_20, A21),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
|
||||
PINMUX_IPSR_GPSR(IP1_27_24, A20),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
|
||||
|
||||
|
|
@ -769,7 +763,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP3_7_4, A10),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP3_11_8, A11),
|
||||
|
|
@ -872,7 +866,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
|
||||
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
|
||||
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
|
||||
PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
|
||||
|
|
@ -953,7 +947,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP6_31_28, D12),
|
||||
|
|
@ -1161,7 +1155,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
|
||||
PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
|
||||
|
|
@ -1190,7 +1184,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
|
||||
PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
|
||||
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
|
||||
|
|
@ -3255,7 +3249,7 @@ static const unsigned int scif0_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
|
||||
};
|
||||
static const unsigned int scif0_ctrl_mux[] = {
|
||||
RTS0_N_TANS_MARK, CTS0_N_MARK,
|
||||
RTS0_N_MARK, CTS0_N_MARK,
|
||||
};
|
||||
/* - SCIF1 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif1_data_a_pins[] = {
|
||||
|
|
@ -3277,7 +3271,7 @@ static const unsigned int scif1_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
|
||||
};
|
||||
static const unsigned int scif1_ctrl_mux[] = {
|
||||
RTS1_N_TANS_MARK, CTS1_N_MARK,
|
||||
RTS1_N_MARK, CTS1_N_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int scif1_data_b_pins[] = {
|
||||
|
|
@ -3329,7 +3323,7 @@ static const unsigned int scif3_ctrl_pins[] = {
|
|||
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
|
||||
};
|
||||
static const unsigned int scif3_ctrl_mux[] = {
|
||||
RTS3_N_TANS_MARK, CTS3_N_MARK,
|
||||
RTS3_N_MARK, CTS3_N_MARK,
|
||||
};
|
||||
static const unsigned int scif3_data_b_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3358,7 +3352,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
|
|||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_a_mux[] = {
|
||||
RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
|
||||
RTS4_N_A_MARK, CTS4_N_A_MARK,
|
||||
};
|
||||
static const unsigned int scif4_data_b_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3379,7 +3373,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
|
|||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_b_mux[] = {
|
||||
RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
|
||||
RTS4_N_B_MARK, CTS4_N_B_MARK,
|
||||
};
|
||||
static const unsigned int scif4_data_c_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3400,7 +3394,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
|
|||
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
};
|
||||
static const unsigned int scif4_ctrl_c_mux[] = {
|
||||
RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
|
||||
RTS4_N_C_MARK, CTS4_N_C_MARK,
|
||||
};
|
||||
/* - SCIF5 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif5_data_a_pins[] = {
|
||||
|
|
@ -5406,11 +5400,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
|
||||
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
|
||||
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
|
||||
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
|
||||
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
|
||||
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
|
||||
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
|
||||
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
|
||||
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
|
||||
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
|
||||
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
|
||||
|
|
@ -5655,11 +5649,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
|
||||
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
|
||||
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
|
||||
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
|
||||
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
|
||||
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
|
||||
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
|
||||
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
|
||||
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
|
||||
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
|
||||
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
|
||||
|
|
|
|||
2329
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
Normal file
2329
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -518,6 +518,8 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_SINGLE(QSPI0_MISO_IO1),
|
||||
PINMUX_SINGLE(QSPI0_MOSI_IO0),
|
||||
PINMUX_SINGLE(QSPI0_SPCLK),
|
||||
PINMUX_SINGLE(SCL0),
|
||||
PINMUX_SINGLE(SDA0),
|
||||
|
||||
/* IPSR0 */
|
||||
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
|
||||
|
|
@ -1057,6 +1059,61 @@ static const unsigned int avb0_avtp_capture_b_mux[] = {
|
|||
AVB0_AVTP_CAPTURE_B_MARK,
|
||||
};
|
||||
|
||||
/* - CAN ------------------------------------------------------------------ */
|
||||
static const unsigned int can0_data_a_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
|
||||
};
|
||||
static const unsigned int can0_data_a_mux[] = {
|
||||
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
|
||||
};
|
||||
static const unsigned int can0_data_b_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int can0_data_b_mux[] = {
|
||||
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
|
||||
};
|
||||
static const unsigned int can1_data_a_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
|
||||
};
|
||||
static const unsigned int can1_data_a_mux[] = {
|
||||
CAN1_TX_A_MARK, CAN1_RX_A_MARK,
|
||||
};
|
||||
static const unsigned int can1_data_b_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
|
||||
};
|
||||
static const unsigned int can1_data_b_mux[] = {
|
||||
CAN1_TX_B_MARK, CAN1_RX_B_MARK,
|
||||
};
|
||||
|
||||
/* - CAN Clock -------------------------------------------------------------- */
|
||||
static const unsigned int can_clk_pins[] = {
|
||||
/* CLK */
|
||||
RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
static const unsigned int can_clk_mux[] = {
|
||||
CAN_CLK_MARK,
|
||||
};
|
||||
|
||||
/* - CAN FD ----------------------------------------------------------------- */
|
||||
static const unsigned int canfd0_data_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
|
||||
};
|
||||
static const unsigned int canfd0_data_mux[] = {
|
||||
CANFD0_TX_MARK, CANFD0_RX_MARK,
|
||||
};
|
||||
static const unsigned int canfd1_data_pins[] = {
|
||||
/* TX, RX */
|
||||
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
|
||||
};
|
||||
static const unsigned int canfd1_data_mux[] = {
|
||||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
/* - I2C -------------------------------------------------------------------- */
|
||||
static const unsigned int i2c0_pins[] = {
|
||||
/* SCL, SDA */
|
||||
|
|
@ -1504,6 +1561,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
|
||||
SH_PFC_PIN_GROUP(avb0_avtp_match_b),
|
||||
SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
|
||||
SH_PFC_PIN_GROUP(can0_data_a),
|
||||
SH_PFC_PIN_GROUP(can0_data_b),
|
||||
SH_PFC_PIN_GROUP(can1_data_a),
|
||||
SH_PFC_PIN_GROUP(can1_data_b),
|
||||
SH_PFC_PIN_GROUP(can_clk),
|
||||
SH_PFC_PIN_GROUP(canfd0_data),
|
||||
SH_PFC_PIN_GROUP(canfd1_data),
|
||||
SH_PFC_PIN_GROUP(i2c0),
|
||||
SH_PFC_PIN_GROUP(i2c1),
|
||||
SH_PFC_PIN_GROUP(i2c2_a),
|
||||
|
|
@ -1581,6 +1645,25 @@ static const char * const avb0_groups[] = {
|
|||
"avb0_avtp_capture_b",
|
||||
};
|
||||
|
||||
static const char * const can0_groups[] = {
|
||||
"can0_data_a",
|
||||
"can0_data_b",
|
||||
};
|
||||
static const char * const can1_groups[] = {
|
||||
"can1_data_a",
|
||||
"can1_data_b",
|
||||
};
|
||||
static const char * const can_clk_groups[] = {
|
||||
"can_clk",
|
||||
};
|
||||
|
||||
static const char * const canfd0_groups[] = {
|
||||
"canfd0_data",
|
||||
};
|
||||
static const char * const canfd1_groups[] = {
|
||||
"canfd1_data",
|
||||
};
|
||||
|
||||
static const char * const i2c0_groups[] = {
|
||||
"i2c0",
|
||||
};
|
||||
|
|
@ -1691,6 +1774,11 @@ static const char * const usb0_groups[] = {
|
|||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
SH_PFC_FUNCTION(can0),
|
||||
SH_PFC_FUNCTION(can1),
|
||||
SH_PFC_FUNCTION(can_clk),
|
||||
SH_PFC_FUNCTION(canfd0),
|
||||
SH_PFC_FUNCTION(canfd1),
|
||||
SH_PFC_FUNCTION(i2c0),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
|
|
|
|||
|
|
@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
|||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
|
||||
|
|
@ -389,10 +390,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
|||
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
||||
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
|
||||
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
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#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
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PORT_GP_CFG_6(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
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#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
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@ -450,9 +455,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
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PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
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#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
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#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
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#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
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PORT_GP_CFG_21(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
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#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
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#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
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PORT_GP_CFG_22(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
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#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
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|
|
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Loading…
Reference in a new issue