dma-mapping: remove the DMA_ATTR_WRITE_BARRIER flag
This flag is not implemented by any backend and only set by the ib_umem module in a single instance. Link: https://lore.kernel.org/r/20191113073214.9514-2-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Jason Gunthorpe <jgg@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>alistair/sunxi64-5.5-dsi
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@ -5,24 +5,6 @@ DMA attributes
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This document describes the semantics of the DMA attributes that are
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This document describes the semantics of the DMA attributes that are
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defined in linux/dma-mapping.h.
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defined in linux/dma-mapping.h.
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DMA_ATTR_WRITE_BARRIER
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----------------------
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DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA
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to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
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all pending DMA writes to complete, and thus provides a mechanism to
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strictly order DMA from a device across all intervening busses and
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bridges. This barrier is not specific to a particular type of
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interconnect, it applies to the system as a whole, and so its
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implementation must account for the idiosyncrasies of the system all
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the way from the DMA device to memory.
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As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
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useful, suppose that a device does a DMA write to indicate that data is
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ready and available in memory. The DMA of the "completion indication"
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could race with data DMA. Mapping the memory used for completion
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indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
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DMA_ATTR_WEAK_ORDERING
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DMA_ATTR_WEAK_ORDERING
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----------------------
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----------------------
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@ -199,7 +199,6 @@ struct ib_umem *ib_umem_get(struct ib_udata *udata, unsigned long addr,
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struct mm_struct *mm;
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struct mm_struct *mm;
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unsigned long npages;
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unsigned long npages;
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int ret;
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int ret;
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unsigned long dma_attrs = 0;
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struct scatterlist *sg;
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struct scatterlist *sg;
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unsigned int gup_flags = FOLL_WRITE;
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unsigned int gup_flags = FOLL_WRITE;
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@ -211,9 +210,6 @@ struct ib_umem *ib_umem_get(struct ib_udata *udata, unsigned long addr,
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if (!context)
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if (!context)
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return ERR_PTR(-EIO);
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return ERR_PTR(-EIO);
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if (dmasync)
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dma_attrs |= DMA_ATTR_WRITE_BARRIER;
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/*
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/*
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* If the combination of the addr and size requested for this memory
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* If the combination of the addr and size requested for this memory
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* region causes an integer overflow, return error.
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* region causes an integer overflow, return error.
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@ -294,11 +290,10 @@ struct ib_umem *ib_umem_get(struct ib_udata *udata, unsigned long addr,
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sg_mark_end(sg);
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sg_mark_end(sg);
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umem->nmap = ib_dma_map_sg_attrs(context->device,
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umem->nmap = ib_dma_map_sg(context->device,
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umem->sg_head.sgl,
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umem->sg_head.sgl,
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umem->sg_nents,
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umem->sg_nents,
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DMA_BIDIRECTIONAL,
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DMA_BIDIRECTIONAL);
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dma_attrs);
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if (!umem->nmap) {
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if (!umem->nmap) {
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ret = -ENOMEM;
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ret = -ENOMEM;
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@ -15,11 +15,8 @@
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/**
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/**
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* List of possible attributes associated with a DMA mapping. The semantics
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* List of possible attributes associated with a DMA mapping. The semantics
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* of each attribute should be defined in Documentation/DMA-attributes.txt.
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* of each attribute should be defined in Documentation/DMA-attributes.txt.
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*
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* DMA_ATTR_WRITE_BARRIER: DMA to a memory region with this attribute
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* forces all pending DMA writes to complete.
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*/
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*/
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#define DMA_ATTR_WRITE_BARRIER (1UL << 0)
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/*
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/*
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* DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping
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* DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping
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* may be weakly ordered, that is that reads and writes may pass each other.
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* may be weakly ordered, that is that reads and writes may pass each other.
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