arm64 fixes for -rc5
- Fix broken SVE ptrace API when running in a big-endian configuration - Fix performance regression due to off-by-one in TLBI range checking - Fix build regression when using Clang -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAl0DsZ0ACgkQt6xw3ITB YzRE3wf9GJibmSnm9q5gmtHcKMrH+atXrI93nyzhBZxYaAYAKSiz7RCMSpc7iudI bGMruaaqn/2xrdOie3vOOfSqFfzrfcFOuh/0id9R2IyiFSg08BrI369buejNRtm+ BUhdUQCe5p5afJ7PYFa7CYD+tSC1WiHXfOhH6sRYllerwaMiR9y/eqf3Gh5zB26Q ca/+2Jh59DxXIpSWP9nTzPyV9xKOJ1B8JdMR5BMIUnOgUXQhMwNeuivRrZnEG9yT PZDGbk5WxKci+LHPOt7stFFuo7hZn3SCKJ0mZ20VUs0w7ETMJuI0Ss4TlE2mgYag TASmsypuLdRz5mxIeyY5QYXppSyYiA== =AhWz -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: "Here are some arm64 fixes for -rc5. The only non-trivial change (in terms of the diffstat) is fixing our SVE ptrace API for big-endian machines, but the majority of this is actually the addition of much-needed comments and updates to the documentation to try to avoid this mess biting us again in future. There are still a couple of small things on the horizon, but nothing major at this point. Summary: - Fix broken SVE ptrace API when running in a big-endian configuration - Fix performance regression due to off-by-one in TLBI range checking - Fix build regression when using Clang" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64/sve: Fix missing SVE/FPSIMD endianness conversions arm64: tlbflush: Ensure start/end of address range are aligned to stride arm64: Don't unconditionally add -Wno-psabi to KBUILD_CFLAGShifive-unleashed-5.2
Linus Torvalds
commit
72a20cee5d
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@ -56,6 +56,18 @@ model features for SVE is included in Appendix A.
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is to connect to a target process first and then attempt a
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ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
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* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
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between userspace and the kernel, the register value is encoded in memory in
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an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
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byte offset i from the start of the memory representation. This affects for
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example the signal frame (struct sve_context) and ptrace interface
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(struct user_sve_header) and associated data.
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Beware that on big-endian systems this results in a different byte order than
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for the FPSIMD V-registers, which are stored as single host-endian 128-bit
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values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
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byte offset i. (struct fpsimd_context, struct user_fpsimd_state).
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2. Vector length terminology
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-----------------------------
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@ -124,6 +136,10 @@ the SVE instruction set architecture.
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size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
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the members.
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* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
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layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
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start of the register's representation in memory.
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* If the SVE context is too big to fit in sigcontext.__reserved[], then extra
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space is allocated on the stack, an extra_context record is written in
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__reserved[] referencing this space. sve_context is then written in the
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@ -51,7 +51,7 @@ endif
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KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
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KBUILD_CFLAGS += -Wno-psabi
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KBUILD_CFLAGS += $(call cc-disable-warning, psabi)
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KBUILD_AFLAGS += $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += $(call cc-option,-mabi=lp64)
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@ -195,6 +195,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
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unsigned long asid = ASID(vma->vm_mm);
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unsigned long addr;
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start = round_down(start, stride);
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end = round_up(end, stride);
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if ((end - start) >= (MAX_TLBI_OPS * stride)) {
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flush_tlb_mm(vma->vm_mm);
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return;
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@ -260,6 +260,13 @@ struct kvm_vcpu_events {
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KVM_REG_SIZE_U256 | \
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((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
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/*
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* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
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* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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* V-registers on big-endian systems: see sigcontext.h for more explanation.
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*/
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#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
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#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
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@ -176,6 +176,10 @@ struct user_sve_header {
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* FPCR uint32_t FPCR
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*
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* Additional data might be appended in the future.
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*
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* The Z-, P- and FFR registers are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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* V-registers on big-endian systems: see sigcontext.h for more explanation.
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*/
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#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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@ -77,6 +77,15 @@ struct fpsimd_context {
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__uint128_t vregs[32];
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};
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/*
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* Note: similarly to all other integer fields, each V-register is stored in an
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* endianness-dependent format, with the byte at offset i from the start of the
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* in-memory representation of the register value containing
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*
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* bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
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* bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
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*/
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/* ESR_EL1 context */
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#define ESR_MAGIC 0x45535201
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@ -204,6 +213,11 @@ struct sve_context {
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* FFR uint16_t[vq] first-fault status register
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*
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* Additional data might be appended in the future.
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*
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* Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
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* is encoded in memory in an endianness-invariant format, with the byte at
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* offset i from the start of the in-memory representation containing bits
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* [(7 + 8 * i) : (8 * i)] of the register value.
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*/
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#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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@ -39,6 +39,7 @@
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sysctl.h>
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#include <linux/swab.h>
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#include <asm/esr.h>
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#include <asm/fpsimd.h>
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@ -352,6 +353,23 @@ static int __init sve_sysctl_init(void) { return 0; }
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#define ZREG(sve_state, vq, n) ((char *)(sve_state) + \
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(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
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#ifdef CONFIG_CPU_BIG_ENDIAN
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static __uint128_t arm64_cpu_to_le128(__uint128_t x)
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{
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u64 a = swab64(x);
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u64 b = swab64(x >> 64);
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return ((__uint128_t)a << 64) | b;
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}
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#else
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static __uint128_t arm64_cpu_to_le128(__uint128_t x)
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{
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return x;
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}
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#endif
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#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
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/*
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* Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
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* task->thread.sve_state.
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@ -369,14 +387,16 @@ static void fpsimd_to_sve(struct task_struct *task)
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void *sst = task->thread.sve_state;
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struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
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unsigned int i;
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__uint128_t *p;
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if (!system_supports_sve())
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return;
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vq = sve_vq_from_vl(task->thread.sve_vl);
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for (i = 0; i < 32; ++i)
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memcpy(ZREG(sst, vq, i), &fst->vregs[i],
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sizeof(fst->vregs[i]));
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for (i = 0; i < 32; ++i) {
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p = (__uint128_t *)ZREG(sst, vq, i);
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*p = arm64_cpu_to_le128(fst->vregs[i]);
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}
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}
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/*
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@ -395,14 +415,16 @@ static void sve_to_fpsimd(struct task_struct *task)
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void const *sst = task->thread.sve_state;
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struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
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unsigned int i;
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__uint128_t const *p;
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if (!system_supports_sve())
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return;
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vq = sve_vq_from_vl(task->thread.sve_vl);
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for (i = 0; i < 32; ++i)
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memcpy(&fst->vregs[i], ZREG(sst, vq, i),
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sizeof(fst->vregs[i]));
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for (i = 0; i < 32; ++i) {
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p = (__uint128_t const *)ZREG(sst, vq, i);
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fst->vregs[i] = arm64_le128_to_cpu(*p);
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}
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}
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#ifdef CONFIG_ARM64_SVE
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@ -491,6 +513,7 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
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void *sst = task->thread.sve_state;
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struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
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unsigned int i;
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__uint128_t *p;
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if (!test_tsk_thread_flag(task, TIF_SVE))
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return;
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@ -499,9 +522,10 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
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memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
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for (i = 0; i < 32; ++i)
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memcpy(ZREG(sst, vq, i), &fst->vregs[i],
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sizeof(fst->vregs[i]));
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for (i = 0; i < 32; ++i) {
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p = (__uint128_t *)ZREG(sst, vq, i);
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*p = arm64_cpu_to_le128(fst->vregs[i]);
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}
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}
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int sve_set_vector_length(struct task_struct *task,
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Loading…
Reference in New Issue