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MLK-23817 gpu: imx: dpu: common: Enable power for dpu irq chip at probe stage 

The dpu common driver creates a irq chip for dpu irqs.
The parent of the irq chip on the i.MX8qm/qxp SoC is the irqsteer.
Since the irqsteer driver may support runtime PM, the dpu common
driver needs to call irq_chip_pm_get/put() where necessary to make
sure power of the irq chip is enabled/disabled properly.  This
patch enables the power at the driver probe stage and disables it
at driver remove stage to achieve basic power management support
for the irq chip.

Suggested-by: Andy Duan <fugang.duan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Liu Ying 2020-04-21 20:12:18 +08:00
parent 5f2beb7ec6
commit 730ecd5db8
2 changed files with 67 additions and 2 deletions
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58
drivers/gpu/imx/dpu/dpu-common.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2019 NXP
* Copyright 2017-2020 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -678,13 +678,69 @@ irq_set_chained_handler_and_data(dpu->irq_##name, dpu_##name##_irq_handler, dpu)
DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_shdload1);
DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_framecomplete1);
#define DPU_IRQ_CHIP_PM_GET(name) \
{ \
ret = irq_chip_pm_get(irq_get_irq_data(dpu->irq_##name)); \
if (ret < 0) { \
dev_err(dpu->dev, \
"failed to get irq chip PM for irq%d %d\n", \
dpu->irq_##name, ret); \
goto pm_get_rollback; \
} \
dpu->irq_chip_pm_get_##name = true; \
}
#define DPU_IRQ_CHIP_PM_PUT_CHECK(name) \
{ \
if (dpu->irq_chip_pm_get_##name) { \
irq_chip_pm_put(irq_get_irq_data(dpu->irq_##name)); \
dpu->irq_chip_pm_get_##name = false; \
} \
}
DPU_IRQ_CHIP_PM_GET(extdst0_shdload);
DPU_IRQ_CHIP_PM_GET(extdst4_shdload);
DPU_IRQ_CHIP_PM_GET(extdst1_shdload);
DPU_IRQ_CHIP_PM_GET(extdst5_shdload);
DPU_IRQ_CHIP_PM_GET(disengcfg_shdload0);
DPU_IRQ_CHIP_PM_GET(disengcfg_framecomplete0);
DPU_IRQ_CHIP_PM_GET(disengcfg_shdload1);
DPU_IRQ_CHIP_PM_GET(disengcfg_framecomplete1);
return 0;
pm_get_rollback:
DPU_IRQ_CHIP_PM_PUT_CHECK(extdst0_shdload);
DPU_IRQ_CHIP_PM_PUT_CHECK(extdst4_shdload);
DPU_IRQ_CHIP_PM_PUT_CHECK(extdst1_shdload);
DPU_IRQ_CHIP_PM_PUT_CHECK(extdst5_shdload);
DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_shdload0);
DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_framecomplete0);
DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_shdload1);
DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_framecomplete1);
return ret;
}
static void dpu_irq_exit(struct dpu_soc *dpu)
{
unsigned int i, irq;
#define DPU_IRQ_CHIP_PM_PUT(name) \
{ \
irq_chip_pm_put(irq_get_irq_data(dpu->irq_##name)); \
dpu->irq_chip_pm_get_##name = false; \
}
DPU_IRQ_CHIP_PM_PUT(extdst0_shdload);
DPU_IRQ_CHIP_PM_PUT(extdst4_shdload);
DPU_IRQ_CHIP_PM_PUT(extdst1_shdload);
DPU_IRQ_CHIP_PM_PUT(extdst5_shdload);
DPU_IRQ_CHIP_PM_PUT(disengcfg_shdload0);
DPU_IRQ_CHIP_PM_PUT(disengcfg_framecomplete0);
DPU_IRQ_CHIP_PM_PUT(disengcfg_shdload1);
DPU_IRQ_CHIP_PM_PUT(disengcfg_framecomplete1);
#define DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(name) \
irq_set_chained_handler_and_data(dpu->irq_##name, NULL, NULL)

11
drivers/gpu/imx/dpu/dpu-prv.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2019 NXP
* Copyright 2017-2020 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -237,6 +237,15 @@ struct dpu_soc {
int irq_disengcfg_framecomplete1;
int irq_line_num;
bool irq_chip_pm_get_extdst0_shdload;
bool irq_chip_pm_get_extdst4_shdload;
bool irq_chip_pm_get_extdst1_shdload;
bool irq_chip_pm_get_extdst5_shdload;
bool irq_chip_pm_get_disengcfg_shdload0;
bool irq_chip_pm_get_disengcfg_framecomplete0;
bool irq_chip_pm_get_disengcfg_shdload1;
bool irq_chip_pm_get_disengcfg_framecomplete1;
struct irq_domain *domain;
struct imx_sc_ipc *dpu_ipc_handle;