bus: ti-sysc: Implement display subsystem reset quirk
The display subsystem (DSS) needs the child outputs disabled for reset. In order to prepare to probe DSS without legacy platform data, let's implement sysc_pre_reset_quirk_dss() similar to what we have for the platform data with omap_dss_reset(). Note that we cannot directly use the old omap_dss_reset() without platform data callbacks and updating omap_dss_reset() to understand struct device. And we will be dropping omap_dss_reset() anyways when all the SoCs are probing with device tree, so let's not mess with the legacy code at all. Cc: Jyri Sarha <jsarha@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -1303,11 +1303,11 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
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SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
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SYSC_QUIRK_CLKDM_NOAUTO),
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SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
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SYSC_QUIRK_OPT_CLKS_IN_RESET),
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SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
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SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
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SYSC_QUIRK_OPT_CLKS_IN_RESET),
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SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
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SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
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SYSC_QUIRK_OPT_CLKS_IN_RESET),
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SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
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SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
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SYSC_QUIRK_CLKDM_NOAUTO),
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SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
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@ -1468,6 +1468,128 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
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}
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}
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/*
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* DSS needs dispc outputs disabled to reset modules. Returns mask of
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* enabled DSS interrupts. Eventually we may be able to do this on
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* dispc init rather than top-level DSS init.
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*/
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static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
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bool disable)
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{
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bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
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const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
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int manager_count;
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bool framedonetv_irq;
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u32 val, irq_mask = 0;
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switch (sysc_soc->soc) {
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case SOC_2420 ... SOC_3630:
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manager_count = 2;
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framedonetv_irq = false;
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break;
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case SOC_4430 ... SOC_4470:
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manager_count = 3;
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break;
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case SOC_5430:
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case SOC_DRA7:
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manager_count = 4;
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break;
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case SOC_AM4:
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manager_count = 1;
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break;
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case SOC_UNKNOWN:
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default:
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return 0;
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};
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/* Remap the whole module range to be able to reset dispc outputs */
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devm_iounmap(ddata->dev, ddata->module_va);
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ddata->module_va = devm_ioremap(ddata->dev,
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ddata->module_pa,
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ddata->module_size);
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if (!ddata->module_va)
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return -EIO;
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/* DISP_CONTROL */
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val = sysc_read(ddata, dispc_offset + 0x40);
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lcd_en = val & lcd_en_mask;
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digit_en = val & digit_en_mask;
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if (lcd_en)
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irq_mask |= BIT(0); /* FRAMEDONE */
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if (digit_en) {
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if (framedonetv_irq)
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irq_mask |= BIT(24); /* FRAMEDONETV */
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else
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irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
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}
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if (disable & (lcd_en | digit_en))
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sysc_write(ddata, dispc_offset + 0x40,
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val & ~(lcd_en_mask | digit_en_mask));
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if (manager_count <= 2)
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return irq_mask;
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/* DISPC_CONTROL2 */
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val = sysc_read(ddata, dispc_offset + 0x238);
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lcd2_en = val & lcd_en_mask;
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if (lcd2_en)
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irq_mask |= BIT(22); /* FRAMEDONE2 */
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if (disable && lcd2_en)
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sysc_write(ddata, dispc_offset + 0x238,
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val & ~lcd_en_mask);
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if (manager_count <= 3)
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return irq_mask;
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/* DISPC_CONTROL3 */
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val = sysc_read(ddata, dispc_offset + 0x848);
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lcd3_en = val & lcd_en_mask;
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if (lcd3_en)
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irq_mask |= BIT(30); /* FRAMEDONE3 */
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if (disable && lcd3_en)
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sysc_write(ddata, dispc_offset + 0x848,
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val & ~lcd_en_mask);
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return irq_mask;
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}
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/* DSS needs child outputs disabled and SDI registers cleared for reset */
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static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
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{
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const int dispc_offset = 0x1000;
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int error;
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u32 irq_mask, val;
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/* Get enabled outputs */
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irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
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if (!irq_mask)
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return;
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/* Clear IRQSTATUS */
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sysc_write(ddata, 0x1000 + 0x18, irq_mask);
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/* Disable outputs */
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val = sysc_quirk_dispc(ddata, dispc_offset, true);
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/* Poll IRQSTATUS */
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error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
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val, val != irq_mask, 100, 50);
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if (error)
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dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
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__func__, val, irq_mask);
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if (sysc_soc->soc == SOC_3430) {
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/* Clear DSS_SDI_CONTROL */
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sysc_write(ddata, dispc_offset + 0x44, 0);
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/* Clear DSS_PLL_CONTROL */
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sysc_write(ddata, dispc_offset + 0x48, 0);
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}
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/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
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sysc_write(ddata, dispc_offset + 0x40, 0);
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}
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/* 1-wire needs module's internal clocks enabled for reset */
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static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
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{
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@ -1606,6 +1728,9 @@ static void sysc_init_module_quirks(struct sysc *ddata)
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if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
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ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
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if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
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ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
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if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
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ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
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ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
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@ -49,6 +49,7 @@ struct sysc_regbits {
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s8 emufree_shift;
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};
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#define SYSC_MODULE_QUIRK_DSS_RESET BIT(23)
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#define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)
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#define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
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#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
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