drm/i915: Use a global lock for modifying global irq flags
We were attempting to use a per-ring spinlock whilst modifying global IRQ flags. A recipe for rare missed interrupts. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -610,17 +610,18 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return false;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (ring->irq_refcount++ == 0) {
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dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return true;
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}
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@ -630,14 +631,15 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (--ring->irq_refcount == 0) {
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dev_priv->gt_irq_mask |= ring->irq_enable_mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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}
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static bool
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@ -645,17 +647,18 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return false;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (ring->irq_refcount++ == 0) {
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dev_priv->irq_mask &= ~ring->irq_enable_mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return true;
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}
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@ -665,14 +668,15 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (--ring->irq_refcount == 0) {
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dev_priv->irq_mask |= ring->irq_enable_mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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}
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static bool
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@ -680,17 +684,18 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return false;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (ring->irq_refcount++ == 0) {
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dev_priv->irq_mask &= ~ring->irq_enable_mask;
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I915_WRITE16(IMR, dev_priv->irq_mask);
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POSTING_READ16(IMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return true;
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}
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@ -700,14 +705,15 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (--ring->irq_refcount == 0) {
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dev_priv->irq_mask |= ring->irq_enable_mask;
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I915_WRITE16(IMR, dev_priv->irq_mask);
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POSTING_READ16(IMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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}
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void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
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@ -786,6 +792,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return false;
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@ -795,14 +802,14 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
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* blt/bsd rings on ivb. */
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gen6_gt_force_wake_get(dev_priv);
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (ring->irq_refcount++ == 0) {
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I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
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dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return true;
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}
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@ -812,15 +819,16 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long flags;
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spin_lock(&ring->irq_lock);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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if (--ring->irq_refcount == 0) {
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I915_WRITE_IMR(ring, ~0);
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dev_priv->gt_irq_mask |= ring->irq_enable_mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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spin_unlock(&ring->irq_lock);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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gen6_gt_force_wake_put(dev_priv);
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}
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@ -954,7 +962,6 @@ static int intel_init_ring_buffer(struct drm_device *dev,
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ring->size = 32 * PAGE_SIZE;
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init_waitqueue_head(&ring->irq_queue);
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spin_lock_init(&ring->irq_lock);
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if (I915_NEED_GFX_HWS(dev)) {
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ret = init_status_page(ring);
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@ -56,8 +56,7 @@ struct intel_ring_buffer {
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*/
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u32 last_retired_head;
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spinlock_t irq_lock;
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u32 irq_refcount;
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u32 irq_refcount; /* protected by dev_priv->irq_lock */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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u32 irq_seqno; /* last seq seem at irq time */
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u32 trace_irq_seqno;
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