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atl1: enable errors and link ints when rx/tx scheduled

Signed-off-by: Tony Zelenoff <antonz@parallels.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Tony Zelenoff 2012-04-13 06:09:52 +00:00 committed by David S. Miller
parent aa45ba90b5
commit 73650f28ae
2 changed files with 30 additions and 14 deletions

View File

@ -2460,20 +2460,33 @@ static int atl1_rings_clean(struct napi_struct *napi, int budget)
napi_complete(napi);
/* re-enable Interrupt */
iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
if (likely(adapter->int_enabled))
atlx_imr_set(adapter, IMR_NORMAL_MASK);
return work_done;
}
static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter)
{
if (likely(napi_schedule_prep(&adapter->napi))) {
__napi_schedule(&adapter->napi);
return 1;
}
if (!napi_schedule_prep(&adapter->napi))
/* It is possible in case even the RX/TX ints are disabled via IMR
* register the ISR bits are set anyway (but do not produce IRQ).
* To handle such situation the napi functions used to check is
* something scheduled or not.
*/
return 0;
dev_printk(KERN_ERR, &adapter->pdev->dev,
"rx: INTs must be disabled!");
return 0;
__napi_schedule(&adapter->napi);
/*
* Disable RX/TX ints via IMR register if it is
* allowed. NAPI handler must reenable them in same
* way.
*/
if (!adapter->int_enabled)
return 1;
atlx_imr_set(adapter, IMR_NORXTX_MASK);
return 1;
}
/*
@ -2538,8 +2551,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
/* transmit or receive event */
if (status & (ISR_CMB_TX | ISR_CMB_RX) &&
atl1_sched_rings_clean(adapter))
/* Go away with INTs disabled */
return IRQ_HANDLED;
break;
/* rx exception */
if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
@ -2551,7 +2563,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
"rx exception, ISR = 0x%x\n",
status);
if (atl1_sched_rings_clean(adapter))
return IRQ_HANDLED;
break;
}
if (--max_ints < 0)

View File

@ -275,13 +275,17 @@ static u32 atl1_check_link(struct atl1_adapter *adapter);
#define ISR_DIS_SMB 0x20000000
#define ISR_DIS_DMA 0x40000000
/* Normal Interrupt mask */
#define IMR_NORMAL_MASK (\
/* Normal Interrupt mask without RX/TX enabled */
#define IMR_NORXTX_MASK (\
ISR_SMB |\
ISR_GPHY |\
ISR_PHY_LINKDOWN|\
ISR_DMAR_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_DMAW_TO_RST)
/* Normal Interrupt mask */
#define IMR_NORMAL_MASK (\
IMR_NORXTX_MASK |\
ISR_CMB_TX |\
ISR_CMB_RX)