* Add pcie, mipi and gen_clk clk ids
* Add audio clk controller clock bindings -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAltEZqMACgkQ5vwPHDfy 2oUaOw//aCV1mCqBCS1S5MfN2Jy7CO23XDFkACIzpIpRa8G1Zp0NlBbKt/aLT5i7 b3Q0HVpamuHN00vWlaJg5oFTgbfTbngsNxP+N26l6sW7fMNkkHfe7oRJGNiWPvhp ehca3lLVjZEh01MxTCTMapblK96QPwI/ErWYNNcfVcbpiOWQAdbFa2PMxVS/5lR7 On7H7erV1HD/I4K2jADBxrn8CMpprEIAPkXq12mhKrQTclQfOFaTzA1dKAJtSDKv lUMiDUroEotZ0Qc3VZtU6XbsA5B9WpCPsyqoK5nKyYGGHJvh2jxJ3cBysuf8wQCo yED/WSn5fAucADC1zOK2NRAnLLT3zOQJqepstN8PjMX91tUpslRbuFCAwVavInsW wXkSyifhpRxgC9wzOYNYuqmHgkQUms2eyktHFcPVElvaQ8CDBg0uH1t5ABQvZM5J bxfAghSx3ThEuMK44b8kp81WizTxQo885ppAPac9pPYqrX0Fm2T7UVlG0V7AVisB t2vKdyA2aliG7AnKRrZ1SAX1BVf80Umw01H+ZI8UQgQBt71d3RLpZAtEll/DI+5L jt18Lahk+Fbs5puwVj0P/kDz9gUhw/jK1lbyI0ArIzD1egmGdfro+omuc+cln3ON qgm9zE2kXRnS0a0T5m2BYHLUJq1IFk7KwOndtEbBnIbqLgCc6lg= =Slkx -----END PGP SIGNATURE----- Merge tag 'meson-clk-dt-for-v4.19' of https://github.com/BayLibre/clk-meson into v4.19/dt64-2 * Add pcie, mipi and gen_clk clk ids * Add audio clk controller clock bindings * tag 'meson-clk-dt-for-v4.19' of https://github.com/BayLibre/clk-meson: clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindingshifive-unleashed-5.1
Kevin Hilman
commit
7382913e23
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@ -0,0 +1,56 @@
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* Amlogic AXG Audio Clock Controllers
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The Amlogic AXG audio clock controller generates and supplies clock to the
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other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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in clock-names.
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- clock-names : must contain the following:
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* "pclk" - Main peripheral bus clock
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may contain the following:
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* "mst_in[0-7]" - 8 input plls to generate clock signals
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* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
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components.
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* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
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components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
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used in device tree sources.
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Example:
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7";
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resets = <&reset RESET_AUDIO>;
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};
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@ -0,0 +1,94 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 Baylibre SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
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#define __AXG_AUDIO_CLKC_BINDINGS_H
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#define AUD_CLKID_SLV_SCLK0 9
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#define AUD_CLKID_SLV_SCLK1 10
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#define AUD_CLKID_SLV_SCLK2 11
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#define AUD_CLKID_SLV_SCLK3 12
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#define AUD_CLKID_SLV_SCLK4 13
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#define AUD_CLKID_SLV_SCLK5 14
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#define AUD_CLKID_SLV_SCLK6 15
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#define AUD_CLKID_SLV_SCLK7 16
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#define AUD_CLKID_SLV_SCLK8 17
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#define AUD_CLKID_SLV_SCLK9 18
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#define AUD_CLKID_SLV_LRCLK0 19
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#define AUD_CLKID_SLV_LRCLK1 20
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#define AUD_CLKID_SLV_LRCLK2 21
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#define AUD_CLKID_SLV_LRCLK3 22
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#define AUD_CLKID_SLV_LRCLK4 23
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#define AUD_CLKID_SLV_LRCLK5 24
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#define AUD_CLKID_SLV_LRCLK6 25
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#define AUD_CLKID_SLV_LRCLK7 26
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#define AUD_CLKID_SLV_LRCLK8 27
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#define AUD_CLKID_SLV_LRCLK9 28
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#define AUD_CLKID_DDR_ARB 29
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#define AUD_CLKID_PDM 30
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#define AUD_CLKID_TDMIN_A 31
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#define AUD_CLKID_TDMIN_B 32
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#define AUD_CLKID_TDMIN_C 33
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#define AUD_CLKID_TDMIN_LB 34
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#define AUD_CLKID_TDMOUT_A 35
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#define AUD_CLKID_TDMOUT_B 36
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#define AUD_CLKID_TDMOUT_C 37
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#define AUD_CLKID_FRDDR_A 38
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#define AUD_CLKID_FRDDR_B 39
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#define AUD_CLKID_FRDDR_C 40
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#define AUD_CLKID_TODDR_A 41
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#define AUD_CLKID_TODDR_B 42
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#define AUD_CLKID_TODDR_C 43
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#define AUD_CLKID_LOOPBACK 44
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#define AUD_CLKID_SPDIFIN 45
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#define AUD_CLKID_SPDIFOUT 46
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#define AUD_CLKID_RESAMPLE 47
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#define AUD_CLKID_POWER_DETECT 48
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#define AUD_CLKID_MST_A_MCLK 49
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#define AUD_CLKID_MST_B_MCLK 50
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#define AUD_CLKID_MST_C_MCLK 51
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#define AUD_CLKID_MST_D_MCLK 52
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#define AUD_CLKID_MST_E_MCLK 53
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#define AUD_CLKID_MST_F_MCLK 54
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#define AUD_CLKID_SPDIFOUT_CLK 55
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#define AUD_CLKID_SPDIFIN_CLK 56
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#define AUD_CLKID_PDM_DCLK 57
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#define AUD_CLKID_PDM_SYSCLK 58
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#define AUD_CLKID_MST_A_SCLK 79
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#define AUD_CLKID_MST_B_SCLK 80
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#define AUD_CLKID_MST_C_SCLK 81
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#define AUD_CLKID_MST_D_SCLK 82
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#define AUD_CLKID_MST_E_SCLK 83
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#define AUD_CLKID_MST_F_SCLK 84
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#define AUD_CLKID_MST_A_LRCLK 86
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#define AUD_CLKID_MST_B_LRCLK 87
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#define AUD_CLKID_MST_C_LRCLK 88
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#define AUD_CLKID_MST_D_LRCLK 89
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#define AUD_CLKID_MST_E_LRCLK 90
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#define AUD_CLKID_MST_F_LRCLK 91
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#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
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#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
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#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
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#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
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#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
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#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
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#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
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#define AUD_CLKID_TDMIN_A_SCLK 123
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#define AUD_CLKID_TDMIN_B_SCLK 124
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#define AUD_CLKID_TDMIN_C_SCLK 125
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#define AUD_CLKID_TDMIN_LB_SCLK 126
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#define AUD_CLKID_TDMOUT_A_SCLK 127
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#define AUD_CLKID_TDMOUT_B_SCLK 128
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#define AUD_CLKID_TDMOUT_C_SCLK 129
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#define AUD_CLKID_TDMIN_A_LRCLK 130
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#define AUD_CLKID_TDMIN_B_LRCLK 131
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#define AUD_CLKID_TDMIN_C_LRCLK 132
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#define AUD_CLKID_TDMIN_LB_LRCLK 133
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#define AUD_CLKID_TDMOUT_A_LRCLK 134
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#define AUD_CLKID_TDMOUT_B_LRCLK 135
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#define AUD_CLKID_TDMOUT_C_LRCLK 136
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
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#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_C_CLK0 60
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#define CLKID_HIFI_PLL 69
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#define CLKID_PCIE_CML_EN0 79
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#define CLKID_PCIE_CML_EN1 80
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#define CLKID_MIPI_ENABLE 81
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#define CLKID_GEN_CLK 84
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#endif /* __AXG_CLKC_H */
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@ -127,5 +127,6 @@
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#define CLKID_VAPB 140
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#define CLKID_VDEC_1 153
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#define CLKID_VDEC_HEVC 156
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#define CLKID_GEN_CLK 159
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#endif /* __GXBB_CLKC_H */
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