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LF-632 clk: s32v234: Fix "enetpll_dfs3" position in sdhc_sels 

According to the RM, MC_CGM_0_AC15_SC[SELCTL] needs to be 0b100 in order to
select ENET PLL DFS 4 as the source for SDHC_CLK. Omitting such a position
in the parents array will prevent clk_get_rate() (called from
sdhci-esdhc-imx.c) from determining the frequency of ipg_clk_perclk.

Fixes: fba4afe476 ("clk: s32v234: Initial enet clk support")
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
(cherry picked from commit 6f47d7ee76d533622f91533d80d7dc2e89583199)
5.4-rM2-2.2.x-imx-squashed
Stefan-Gabriel Mirea 2020-01-14 18:34:01 +02:00 committed by Jason Liu
parent ae43adb972
commit 7392a4f58d
1 changed files with 1 additions and 1 deletions
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drivers/clk/s32/s32v234/clk.c
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@ -31,7 +31,7 @@ PNAME(lin_sels) = {"firc", "fxosc", "dummy",
"periphpll_phi0_div3", "dummy", "dummy",
"dummy", "dummy", "sys6",};
PNAME(sdhc_sels) = {"firc", "fxosc", "dummy",
PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy",
"enetpll_dfs3",};
PNAME(enet_sels) = {"firc", "fxosc", "dummy",