drm/i915/icl: WaForwardProgressSoftReset
Avoids a hang during soft reset. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Which steppings affected by this are not clear. For the moment, apply unconditionally as per the BSpec (Mika) - Add reference to another HSD also related References: HSDES#1405476379 References: HSDES#2006612137 Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-14-git-send-email-oscar.mateo@intel.com
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@ -9897,6 +9897,11 @@ enum skl_power_gate {
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/* Media decoder 2 MOCS registers */
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#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
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#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
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#define PMFLUSHDONE_LNICRSDROP (1 << 20)
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#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
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#define PMFLUSHDONE_LNEBLK (1 << 22)
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/* gamt regs */
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#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
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#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
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@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
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I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
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I915_READ(INF_UNIT_LEVEL_CLKGATE) |
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CGPSF_CLKGATE_DIS);
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/* WaForwardProgressSoftReset:icl */
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I915_WRITE(GEN10_SCRATCH_LNCF2,
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I915_READ(GEN10_SCRATCH_LNCF2) |
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PMFLUSHDONE_LNICRSDROP |
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PMFLUSH_GAPL3UNBLOCK |
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PMFLUSHDONE_LNEBLK);
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}
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void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
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