mailbox: imx: add support for imx v1 mu
There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>5.4-rM2-2.2.x-imx-squashed
Richard Zhu
Dong Aisheng
parent
adecb130af
commit
7422980717
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@ -12,19 +12,11 @@
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#include <linux/of_device.h>
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#include <linux/slab.h>
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/* Transmit Register */
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#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
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/* Receive Register */
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#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
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/* Status Register */
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#define IMX_MU_xSR 0x20
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#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
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#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
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#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
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#define IMX_MU_xSR_BRDIP BIT(9)
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/* Control Register */
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#define IMX_MU_xCR 0x24
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
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/* Receive Interrupt Enable */
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@ -44,6 +36,13 @@ enum imx_mu_chan_type {
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IMX_MU_TYPE_RXDB, /* Rx doorbell */
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};
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struct imx_mu_dcfg {
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u32 xTR[4]; /* Transmit Registers */
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u32 xRR[4]; /* Receive Registers */
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u32 xSR; /* Status Register */
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u32 xCR; /* Control Register */
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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@ -61,6 +60,7 @@ struct imx_mu_priv {
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struct mbox_chan mbox_chans[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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const struct imx_mu_dcfg *dcfg;
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struct clk *clk;
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int irq;
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@ -70,6 +70,20 @@ struct imx_mu_priv {
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bool side_b;
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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.xSR = 0x20,
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.xCR = 0x24,
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.xTR = {0x20, 0x24, 0x28, 0x2c},
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.xRR = {0x40, 0x44, 0x48, 0x4c},
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.xSR = 0x60,
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.xCR = 0x64,
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};
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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@ -91,10 +105,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
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u32 val;
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spin_lock_irqsave(&priv->xcr_lock, flags);
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val = imx_mu_read(priv, IMX_MU_xCR);
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val = imx_mu_read(priv, priv->dcfg->xCR);
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val &= ~clr;
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val |= set;
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imx_mu_write(priv, val, IMX_MU_xCR);
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imx_mu_write(priv, val, priv->dcfg->xCR);
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spin_unlock_irqrestore(&priv->xcr_lock, flags);
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return val;
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@ -114,8 +128,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 val, ctrl, dat;
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ctrl = imx_mu_read(priv, IMX_MU_xCR);
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val = imx_mu_read(priv, IMX_MU_xSR);
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ctrl = imx_mu_read(priv, priv->dcfg->xCR);
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val = imx_mu_read(priv, priv->dcfg->xSR);
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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@ -141,10 +155,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
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mbox_chan_txdone(chan, 0);
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
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dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
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mbox_chan_received_data(chan, (void *)&dat);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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mbox_chan_received_data(chan, NULL);
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} else {
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
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@ -162,7 +176,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data)
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
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imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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@ -273,7 +287,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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return;
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/* Set default MU configuration */
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imx_mu_write(priv, 0, IMX_MU_xCR);
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imx_mu_write(priv, 0, priv->dcfg->xCR);
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}
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static int imx_mu_probe(struct platform_device *pdev)
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@ -281,6 +295,7 @@ static int imx_mu_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct imx_mu_priv *priv;
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const struct imx_mu_dcfg *dcfg;
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unsigned int i;
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int ret;
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@ -298,6 +313,11 @@ static int imx_mu_probe(struct platform_device *pdev)
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if (priv->irq < 0)
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return priv->irq;
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dcfg = of_device_get_match_data(dev);
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if (!dcfg)
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return -EINVAL;
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priv->dcfg = dcfg;
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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if (PTR_ERR(priv->clk) != -ENOENT)
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@ -354,7 +374,7 @@ static int imx_mu_suspend_noirq(struct device *dev)
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{
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struct imx_mu_priv *priv = dev_get_drvdata(dev);
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priv->xcr = imx_mu_read(priv, IMX_MU_xCR);
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priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
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return 0;
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}
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@ -363,7 +383,7 @@ static int imx_mu_resume_noirq(struct device *dev)
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{
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struct imx_mu_priv *priv = dev_get_drvdata(dev);
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imx_mu_write(priv, priv->xcr, IMX_MU_xCR);
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imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
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return 0;
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}
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@ -374,7 +394,8 @@ static const struct dev_pm_ops imx_mu_pm_ops = {
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};
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx6sx-mu" },
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
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