clk: mmp2: fix link error without mmp2
The newly added function is only built into the kernel if mmp2
is enabled, causing a link error otherwise.
arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks':
clk.c:(.text+0x6dc): undefined reference to `mmp_clk_register_pll'
Move it to a different file to get it to link.
Fixes: 5d34d0b32d
("clk: mmp2: Add support for PLL clock sources")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200408160518.2798571-1-arnd@arndb.de
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
924ed1f5c1
commit
742b50f9dc
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@ -97,7 +97,7 @@ static const struct clk_ops mmp_clk_pll_ops = {
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.recalc_rate = mmp_clk_pll_recalc_rate,
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};
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struct clk *mmp_clk_register_pll(char *name,
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static struct clk *mmp_clk_register_pll(char *name,
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unsigned long default_rate,
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void __iomem *enable_reg, u32 enable,
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void __iomem *reg, u8 shift,
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@ -137,3 +137,34 @@ struct clk *mmp_clk_register_pll(char *name,
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return clk;
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}
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void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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void __iomem *reg = NULL;
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if (clks[i].offset)
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reg = base + clks[i].offset;
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clk = mmp_clk_register_pll(clks[i].name,
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clks[i].default_rate,
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base + clks[i].enable_offset,
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clks[i].enable,
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reg, clks[i].shift,
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clks[i].input_rate,
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base + clks[i].postdiv_offset,
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clks[i].postdiv_shift);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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@ -176,37 +176,6 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit,
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}
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}
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void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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void __iomem *reg = NULL;
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if (clks[i].offset)
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reg = base + clks[i].offset;
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clk = mmp_clk_register_pll(clks[i].name,
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clks[i].default_rate,
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base + clks[i].enable_offset,
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clks[i].enable,
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reg, clks[i].shift,
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clks[i].input_rate,
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base + clks[i].postdiv_offset,
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clks[i].postdiv_shift);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
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struct clk *clk)
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{
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@ -238,13 +238,6 @@ void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size);
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extern struct clk *mmp_clk_register_pll(char *name,
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unsigned long default_rate,
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void __iomem *enable_reg, u32 enable,
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void __iomem *reg, u8 shift,
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unsigned long input_rate,
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void __iomem *postdiv_reg, u8 postdiv_shift);
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#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
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{ \
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.width_div = (w_d), \
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