lib/raid6/altivec: Add vpermxor implementation for raid6 Q syndrome
This patch uses the vpermxor instruction to optimise the raid6 Q syndrome. This instruction was made available with POWER8, ISA version 2.07. It allows for both vperm and vxor instructions to be done in a single instruction. This has been tested for correctness on a ppc64le vm with a basic RAID6 setup containing 5 drives. The performance benchmarks are from the raid6test in the /lib/raid6/test directory. These results are from an IBM Firestone machine with ppc64le architecture. The benchmark results show a 35% speed increase over the best existing algorithm for powerpc (altivec). The raid6test has also been run on a big-endian ppc64 vm to ensure it also works for big-endian architectures. Performance benchmarks: raid6: altivecx4 gen() 18773 MB/s raid6: altivecx8 gen() 19438 MB/s raid6: vpermxor4 gen() 25112 MB/s raid6: vpermxor8 gen() 26279 MB/s Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Daniel Axtens <dja@axtens.net> [mpe: Add VPERMXOR macro so we can build with old binutils] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Matt Brown
Michael Ellerman
parent
7004263bd4
commit
751ba79cc5
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@ -271,6 +271,7 @@
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#define PPC_INST_TLBSRX_DOT 0x7c0006a5
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#define PPC_INST_VPMSUMW 0x10000488
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#define PPC_INST_VPMSUMD 0x100004c8
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#define PPC_INST_VPERMXOR 0x1000002d
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#define PPC_INST_XXLOR 0xf0000490
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#define PPC_INST_XXSWAPD 0xf0000250
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#define PPC_INST_XVCPSGNDP 0xf0000780
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@ -517,6 +518,11 @@
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#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
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VSX_XX3((t), (a), (b))))
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#define VPERMXOR(vrt, vra, vrb, vrc) \
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stringify_in_c(.long (PPC_INST_VPERMXOR | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
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#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
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#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
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#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
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@ -107,6 +107,10 @@ extern const struct raid6_calls raid6_avx512x2;
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extern const struct raid6_calls raid6_avx512x4;
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extern const struct raid6_calls raid6_tilegx8;
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extern const struct raid6_calls raid6_s390vx8;
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extern const struct raid6_calls raid6_vpermxor1;
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extern const struct raid6_calls raid6_vpermxor2;
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extern const struct raid6_calls raid6_vpermxor4;
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extern const struct raid6_calls raid6_vpermxor8;
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struct raid6_recov_calls {
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void (*data2)(int, size_t, int, int, void **);
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@ -4,3 +4,4 @@ int*.c
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tables.c
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neon?.c
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s390vx?.c
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vpermxor*.c
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@ -5,7 +5,8 @@ raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \
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int8.o int16.o int32.o
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raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o recov_avx512.o
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raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o
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raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o \
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vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o
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raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o
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raid6_pq-$(CONFIG_TILEGX) += tilegx8.o
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raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o
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@ -91,6 +92,30 @@ $(obj)/altivec8.c: UNROLL := 8
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$(obj)/altivec8.c: $(src)/altivec.uc $(src)/unroll.awk FORCE
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$(call if_changed,unroll)
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CFLAGS_vpermxor1.o += $(altivec_flags)
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targets += vpermxor1.c
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$(obj)/vpermxor1.c: UNROLL := 1
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$(obj)/vpermxor1.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE
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$(call if_changed,unroll)
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CFLAGS_vpermxor2.o += $(altivec_flags)
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targets += vpermxor2.c
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$(obj)/vpermxor2.c: UNROLL := 2
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$(obj)/vpermxor2.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE
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$(call if_changed,unroll)
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CFLAGS_vpermxor4.o += $(altivec_flags)
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targets += vpermxor4.c
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$(obj)/vpermxor4.c: UNROLL := 4
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$(obj)/vpermxor4.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE
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$(call if_changed,unroll)
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CFLAGS_vpermxor8.o += $(altivec_flags)
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targets += vpermxor8.c
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$(obj)/vpermxor8.c: UNROLL := 8
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$(obj)/vpermxor8.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE
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$(call if_changed,unroll)
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CFLAGS_neon1.o += $(NEON_FLAGS)
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targets += neon1.c
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$(obj)/neon1.c: UNROLL := 1
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@ -74,6 +74,10 @@ const struct raid6_calls * const raid6_algos[] = {
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&raid6_altivec2,
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&raid6_altivec4,
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&raid6_altivec8,
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&raid6_vpermxor1,
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&raid6_vpermxor2,
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&raid6_vpermxor4,
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&raid6_vpermxor8,
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#endif
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#if defined(CONFIG_TILEGX)
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&raid6_tilegx8,
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@ -48,7 +48,8 @@ else
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gcc -c -x c - >&/dev/null && \
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rm ./-.o && echo yes)
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ifeq ($(HAS_ALTIVEC),yes)
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OBJS += altivec1.o altivec2.o altivec4.o altivec8.o
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OBJS += altivec1.o altivec2.o altivec4.o altivec8.o \
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vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o
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endif
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endif
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ifeq ($(ARCH),tilegx)
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@ -98,6 +99,18 @@ altivec4.c: altivec.uc ../unroll.awk
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altivec8.c: altivec.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=8 < altivec.uc > $@
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vpermxor1.c: vpermxor.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=1 < vpermxor.uc > $@
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vpermxor2.c: vpermxor.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=2 < vpermxor.uc > $@
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vpermxor4.c: vpermxor.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=4 < vpermxor.uc > $@
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vpermxor8.c: vpermxor.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=8 < vpermxor.uc > $@
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int1.c: int.uc ../unroll.awk
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$(AWK) ../unroll.awk -vN=1 < int.uc > $@
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@ -123,7 +136,7 @@ tables.c: mktables
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./mktables > tables.c
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clean:
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rm -f *.o *.a mktables mktables.c *.uc int*.c altivec*.c neon*.c tables.c raid6test
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rm -f *.o *.a mktables mktables.c *.uc int*.c altivec*.c vpermxor*.c neon*.c tables.c raid6test
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rm -f tilegx*.c
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spotless: clean
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@ -0,0 +1,105 @@
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/*
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* Copyright 2017, Matt Brown, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* vpermxor$#.c
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*
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* Based on H. Peter Anvin's paper - The mathematics of RAID-6
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*
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* $#-way unrolled portable integer math RAID-6 instruction set
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* This file is postprocessed using unroll.awk
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*
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* vpermxor$#.c makes use of the vpermxor instruction to optimise the RAID6 Q
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* syndrome calculations.
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* This can be run on systems which have both Altivec and vpermxor instruction.
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*
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* This instruction was introduced in POWER8 - ISA v2.07.
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*/
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#include <linux/raid/pq.h>
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#ifdef CONFIG_ALTIVEC
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#include <altivec.h>
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#ifdef __KERNEL__
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#include <asm/cputable.h>
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#include <asm/ppc-opcode.h>
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#include <asm/switch_to.h>
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#endif
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typedef vector unsigned char unative_t;
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#define NSIZE sizeof(unative_t)
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static const vector unsigned char gf_low = {0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14,
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0x12, 0x10, 0x0e, 0x0c, 0x0a, 0x08,
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0x06, 0x04, 0x02,0x00};
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static const vector unsigned char gf_high = {0xfd, 0xdd, 0xbd, 0x9d, 0x7d, 0x5d,
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0x3d, 0x1d, 0xe0, 0xc0, 0xa0, 0x80,
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0x60, 0x40, 0x20, 0x00};
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static void noinline raid6_vpermxor$#_gen_syndrome_real(int disks, size_t bytes,
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void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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unative_t wp$$, wq$$, wd$$;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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for (d = 0; d < bytes; d += NSIZE*$#) {
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wp$$ = wq$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
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for (z = z0-1; z>=0; z--) {
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wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
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/* P syndrome */
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wp$$ = vec_xor(wp$$, wd$$);
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/* Q syndrome */
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asm(VPERMXOR(%0,%1,%2,%3):"=v"(wq$$):"v"(gf_high), "v"(gf_low), "v"(wq$$));
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wq$$ = vec_xor(wq$$, wd$$);
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}
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*(unative_t *)&p[d+NSIZE*$$] = wp$$;
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*(unative_t *)&q[d+NSIZE*$$] = wq$$;
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}
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}
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static void raid6_vpermxor$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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preempt_disable();
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enable_kernel_altivec();
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raid6_vpermxor$#_gen_syndrome_real(disks, bytes, ptrs);
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disable_kernel_altivec();
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preempt_enable();
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}
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int raid6_have_altivec_vpermxor(void);
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#if $# == 1
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int raid6_have_altivec_vpermxor(void)
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{
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/* Check if arch has both altivec and the vpermxor instructions */
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# ifdef __KERNEL__
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return (cpu_has_feature(CPU_FTR_ALTIVEC_COMP) &&
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cpu_has_feature(CPU_FTR_ARCH_207S));
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# else
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return 1;
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#endif
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}
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#endif
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const struct raid6_calls raid6_vpermxor$# = {
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raid6_vpermxor$#_gen_syndrome,
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NULL,
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raid6_have_altivec_vpermxor,
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"vpermxor$#",
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0
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};
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#endif
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