drm/amd/display: Fix update type for multiple planes
[Why] determine_update_type_for_commit() uses pointers to single instance of local variable to fill scaling/color info for all planes updates. This is a bug, that leads to incorrect update type for commit in case of multiple planes per crtc. Each plane should refer to separate scaling/color data. [How] Use arrays for plane properties. Bundle all properties into a single structure to simplify memory allocation. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -7759,24 +7759,27 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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struct drm_crtc_state *new_crtc_state, *old_crtc_state;
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struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
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struct dc_stream_status *status = NULL;
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struct dc_surface_update *updates;
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enum surface_update_type update_type = UPDATE_TYPE_FAST;
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struct surface_info_bundle {
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struct dc_surface_update surface_updates[MAX_SURFACES];
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struct dc_plane_info plane_infos[MAX_SURFACES];
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struct dc_scaling_info scaling_infos[MAX_SURFACES];
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struct dc_flip_addrs flip_addrs[MAX_SURFACES];
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struct dc_stream_update stream_update;
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} *bundle;
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updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
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bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
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if (!updates) {
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DRM_ERROR("Failed to allocate plane updates\n");
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if (!bundle) {
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DRM_ERROR("Failed to allocate update bundle\n");
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/* Set type to FULL to avoid crashing in DC*/
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update_type = UPDATE_TYPE_FULL;
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goto cleanup;
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}
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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struct dc_scaling_info scaling_info;
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struct dc_stream_update stream_update;
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memset(&stream_update, 0, sizeof(stream_update));
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memset(bundle, 0, sizeof(struct surface_info_bundle));
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new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
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old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
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@ -7793,8 +7796,9 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
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const struct amdgpu_framebuffer *amdgpu_fb =
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to_amdgpu_framebuffer(new_plane_state->fb);
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struct dc_plane_info plane_info;
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struct dc_flip_addrs flip_addr;
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struct dc_plane_info *plane_info = &bundle->plane_infos[num_plane];
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struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane];
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struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane];
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uint64_t tiling_flags;
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new_plane_crtc = new_plane_state->crtc;
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@ -7812,49 +7816,48 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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if (crtc != new_plane_crtc)
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continue;
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updates[num_plane].surface = new_dm_plane_state->dc_state;
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bundle->surface_updates[num_plane].surface =
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new_dm_plane_state->dc_state;
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if (new_crtc_state->mode_changed) {
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stream_update.dst = new_dm_crtc_state->stream->dst;
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stream_update.src = new_dm_crtc_state->stream->src;
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bundle->stream_update.dst = new_dm_crtc_state->stream->dst;
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bundle->stream_update.src = new_dm_crtc_state->stream->src;
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}
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if (new_crtc_state->color_mgmt_changed) {
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updates[num_plane].gamma =
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bundle->surface_updates[num_plane].gamma =
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new_dm_plane_state->dc_state->gamma_correction;
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updates[num_plane].in_transfer_func =
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bundle->surface_updates[num_plane].in_transfer_func =
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new_dm_plane_state->dc_state->in_transfer_func;
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stream_update.gamut_remap =
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bundle->stream_update.gamut_remap =
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&new_dm_crtc_state->stream->gamut_remap_matrix;
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stream_update.output_csc_transform =
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bundle->stream_update.output_csc_transform =
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&new_dm_crtc_state->stream->csc_color_matrix;
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stream_update.out_transfer_func =
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bundle->stream_update.out_transfer_func =
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new_dm_crtc_state->stream->out_transfer_func;
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}
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ret = fill_dc_scaling_info(new_plane_state,
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&scaling_info);
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scaling_info);
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if (ret)
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goto cleanup;
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updates[num_plane].scaling_info = &scaling_info;
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bundle->surface_updates[num_plane].scaling_info = scaling_info;
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if (amdgpu_fb) {
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ret = get_fb_info(amdgpu_fb, &tiling_flags);
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if (ret)
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goto cleanup;
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memset(&flip_addr, 0, sizeof(flip_addr));
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ret = fill_dc_plane_info_and_addr(
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dm->adev, new_plane_state, tiling_flags,
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&plane_info,
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&flip_addr.address);
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plane_info,
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&flip_addr->address);
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if (ret)
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goto cleanup;
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updates[num_plane].plane_info = &plane_info;
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updates[num_plane].flip_addr = &flip_addr;
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bundle->surface_updates[num_plane].plane_info = plane_info;
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bundle->surface_updates[num_plane].flip_addr = flip_addr;
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}
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num_plane++;
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@ -7875,14 +7878,15 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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status = dc_stream_get_status_from_state(old_dm_state->context,
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new_dm_crtc_state->stream);
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stream_update.stream = new_dm_crtc_state->stream;
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bundle->stream_update.stream = new_dm_crtc_state->stream;
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/*
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* TODO: DC modifies the surface during this call so we need
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* to lock here - find a way to do this without locking.
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*/
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mutex_lock(&dm->dc_lock);
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update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
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&stream_update, status);
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update_type = dc_check_update_surfaces_for_stream(
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dc, bundle->surface_updates, num_plane,
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&bundle->stream_update, status);
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mutex_unlock(&dm->dc_lock);
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if (update_type > UPDATE_TYPE_MED) {
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@ -7892,7 +7896,7 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
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}
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cleanup:
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kfree(updates);
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kfree(bundle);
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*out_type = update_type;
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return ret;
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