dt-bindings: firmware: imx: Move system control into dt-binding headfile

i.MX8 SoCs DTS file needs system control macro definitions, so move them
into dt-binding headfile, then include/linux/firmware/imx/types.h can be
removed and those drivers using it should be changed accordingly.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Dong Aisheng 2020-04-26 16:11:43 +08:00 committed by Shawn Guo
parent f5f27b79ea
commit 755a739794
5 changed files with 52 additions and 68 deletions

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@ -8,7 +8,6 @@
*/
#include <linux/err.h>
#include <linux/firmware/imx/types.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/sci.h>
#include <linux/interrupt.h>

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@ -3,9 +3,9 @@
* Copyright 2018-2020 NXP.
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/firmware/imx/types.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>

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@ -547,4 +547,55 @@
#define IMX_SC_R_ATTESTATION 545
#define IMX_SC_R_LAST 546
/*
* Defines for SC CONTROL
*/
#define IMX_SC_C_TEMP 0
#define IMX_SC_C_TEMP_HI 1
#define IMX_SC_C_TEMP_LOW 2
#define IMX_SC_C_PXL_LINK_MST1_ADDR 3
#define IMX_SC_C_PXL_LINK_MST2_ADDR 4
#define IMX_SC_C_PXL_LINK_MST_ENB 5
#define IMX_SC_C_PXL_LINK_MST1_ENB 6
#define IMX_SC_C_PXL_LINK_MST2_ENB 7
#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8
#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9
#define IMX_SC_C_PXL_LINK_MST_VLD 10
#define IMX_SC_C_PXL_LINK_MST1_VLD 11
#define IMX_SC_C_PXL_LINK_MST2_VLD 12
#define IMX_SC_C_SINGLE_MODE 13
#define IMX_SC_C_ID 14
#define IMX_SC_C_PXL_CLK_POLARITY 15
#define IMX_SC_C_LINESTATE 16
#define IMX_SC_C_PCIE_G_RST 17
#define IMX_SC_C_PCIE_BUTTON_RST 18
#define IMX_SC_C_PCIE_PERST 19
#define IMX_SC_C_PHY_RESET 20
#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21
#define IMX_SC_C_PANIC 22
#define IMX_SC_C_PRIORITY_GROUP 23
#define IMX_SC_C_TXCLK 24
#define IMX_SC_C_CLKDIV 25
#define IMX_SC_C_DISABLE_50 26
#define IMX_SC_C_DISABLE_125 27
#define IMX_SC_C_SEL_125 28
#define IMX_SC_C_MODE 29
#define IMX_SC_C_SYNC_CTRL0 30
#define IMX_SC_C_KACHUNK_CNT 31
#define IMX_SC_C_KACHUNK_SEL 32
#define IMX_SC_C_SYNC_CTRL1 33
#define IMX_SC_C_DPI_RESET 34
#define IMX_SC_C_MIPI_RESET 35
#define IMX_SC_C_DUAL_MODE 36
#define IMX_SC_C_VOLTAGE 37
#define IMX_SC_C_PXL_LINK_SEL 38
#define IMX_SC_C_OFS_SEL 39
#define IMX_SC_C_OFS_AUDIO 40
#define IMX_SC_C_OFS_PERIPH 41
#define IMX_SC_C_OFS_IRQ 42
#define IMX_SC_C_RST0 43
#define IMX_SC_C_RST1 44
#define IMX_SC_C_SEL0 45
#define IMX_SC_C_LAST 46
#endif /* __DT_BINDINGS_RSCRC_IMX_H */

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@ -11,7 +11,6 @@
#define _SC_SCI_H
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/types.h>
#include <linux/firmware/imx/svc/misc.h>
#include <linux/firmware/imx/svc/pm.h>

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@ -1,65 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017~2018 NXP
*
* Header file containing types used across multiple service APIs.
*/
#ifndef _SC_TYPES_H
#define _SC_TYPES_H
/*
* This type is used to indicate a control.
*/
enum imx_sc_ctrl {
IMX_SC_C_TEMP = 0,
IMX_SC_C_TEMP_HI = 1,
IMX_SC_C_TEMP_LOW = 2,
IMX_SC_C_PXL_LINK_MST1_ADDR = 3,
IMX_SC_C_PXL_LINK_MST2_ADDR = 4,
IMX_SC_C_PXL_LINK_MST_ENB = 5,
IMX_SC_C_PXL_LINK_MST1_ENB = 6,
IMX_SC_C_PXL_LINK_MST2_ENB = 7,
IMX_SC_C_PXL_LINK_SLV1_ADDR = 8,
IMX_SC_C_PXL_LINK_SLV2_ADDR = 9,
IMX_SC_C_PXL_LINK_MST_VLD = 10,
IMX_SC_C_PXL_LINK_MST1_VLD = 11,
IMX_SC_C_PXL_LINK_MST2_VLD = 12,
IMX_SC_C_SINGLE_MODE = 13,
IMX_SC_C_ID = 14,
IMX_SC_C_PXL_CLK_POLARITY = 15,
IMX_SC_C_LINESTATE = 16,
IMX_SC_C_PCIE_G_RST = 17,
IMX_SC_C_PCIE_BUTTON_RST = 18,
IMX_SC_C_PCIE_PERST = 19,
IMX_SC_C_PHY_RESET = 20,
IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21,
IMX_SC_C_PANIC = 22,
IMX_SC_C_PRIORITY_GROUP = 23,
IMX_SC_C_TXCLK = 24,
IMX_SC_C_CLKDIV = 25,
IMX_SC_C_DISABLE_50 = 26,
IMX_SC_C_DISABLE_125 = 27,
IMX_SC_C_SEL_125 = 28,
IMX_SC_C_MODE = 29,
IMX_SC_C_SYNC_CTRL0 = 30,
IMX_SC_C_KACHUNK_CNT = 31,
IMX_SC_C_KACHUNK_SEL = 32,
IMX_SC_C_SYNC_CTRL1 = 33,
IMX_SC_C_DPI_RESET = 34,
IMX_SC_C_MIPI_RESET = 35,
IMX_SC_C_DUAL_MODE = 36,
IMX_SC_C_VOLTAGE = 37,
IMX_SC_C_PXL_LINK_SEL = 38,
IMX_SC_C_OFS_SEL = 39,
IMX_SC_C_OFS_AUDIO = 40,
IMX_SC_C_OFS_PERIPH = 41,
IMX_SC_C_OFS_IRQ = 42,
IMX_SC_C_RST0 = 43,
IMX_SC_C_RST1 = 44,
IMX_SC_C_SEL0 = 45,
IMX_SC_C_LAST
};
#endif /* _SC_TYPES_H */