ARM: OMAP2+: Drop sdma interrupt handling for mach-omap2
All device tree probing omap SoCs only have device drivers that are using Linux dmaengine API with the IRQENABLE_L1 interrupts. Only omap1 is still using old legacy dma. This means we can remove the legacy sdma interrupt handling for IRQENABLE_L0, and only rely on the dmaengine driver using IRQENABLE_L1. The legacy code still allocates the channels, but that will be deal with in the following patches. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Vinod Koul <vkoul@kernel.org> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>alistair/sensors
Tony Lindgren
parent
28b5afcd06
commit
755cbfd8cf
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@ -272,9 +272,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
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if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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d->dev_caps |= HS_CHANNELS_RESERVED;
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if (platform_get_irq_byname(pdev, "0") < 0)
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d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
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/* Check the capabilities register for descriptor loading feature */
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if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
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dma_common_ch_end = CCDN;
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@ -88,22 +88,6 @@ struct dma_link_info {
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};
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static struct dma_link_info *dma_linked_lch;
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#ifndef CONFIG_ARCH_OMAP1
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/* Chain handling macros */
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#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
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(0 == dma_linked_lch[chain_id].q_count)
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#define __OMAP_DMA_CHAIN_INCQ(end) \
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((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
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#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
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do { \
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__OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
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dma_linked_lch[chain_id].q_count--; \
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} while (0)
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#endif
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static int dma_lch_count;
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static int dma_chan_count;
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static int omap_dma_reserve_channels;
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@ -469,12 +453,6 @@ static inline void enable_lnk(int lch)
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if (dma_chan[lch].next_lch != -1)
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l = dma_chan[lch].next_lch | (1 << 15);
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#ifndef CONFIG_ARCH_OMAP1
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if (dma_omap2plus())
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if (dma_chan[lch].next_linked_ch != -1)
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l = dma_chan[lch].next_linked_ch | (1 << 15);
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#endif
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p->dma_write(l, CLNK_CTRL, lch);
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}
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@ -501,42 +479,6 @@ static inline void disable_lnk(int lch)
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dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
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}
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static inline void omap2_enable_irq_lch(int lch)
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{
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u32 val;
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unsigned long flags;
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if (dma_omap1())
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return;
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spin_lock_irqsave(&dma_chan_lock, flags);
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/* clear IRQ STATUS */
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p->dma_write(1 << lch, IRQSTATUS_L0, lch);
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/* Enable interrupt */
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val = p->dma_read(IRQENABLE_L0, lch);
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val |= 1 << lch;
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p->dma_write(val, IRQENABLE_L0, lch);
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spin_unlock_irqrestore(&dma_chan_lock, flags);
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}
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static inline void omap2_disable_irq_lch(int lch)
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{
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u32 val;
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unsigned long flags;
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if (dma_omap1())
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return;
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spin_lock_irqsave(&dma_chan_lock, flags);
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/* Disable interrupt */
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val = p->dma_read(IRQENABLE_L0, lch);
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val &= ~(1 << lch);
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p->dma_write(val, IRQENABLE_L0, lch);
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/* clear IRQ STATUS */
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p->dma_write(1 << lch, IRQSTATUS_L0, lch);
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spin_unlock_irqrestore(&dma_chan_lock, flags);
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}
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int omap_request_dma(int dev_id, const char *dev_name,
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void (*callback)(int lch, u16 ch_status, void *data),
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void *data, int *dma_ch_out)
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@ -565,9 +507,6 @@ int omap_request_dma(int dev_id, const char *dev_name,
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if (p->clear_lch_regs)
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p->clear_lch_regs(free_ch);
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if (dma_omap2plus())
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omap_clear_dma(free_ch);
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spin_unlock_irqrestore(&dma_chan_lock, flags);
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chan->dev_name = dev_name;
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@ -575,20 +514,10 @@ int omap_request_dma(int dev_id, const char *dev_name,
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chan->data = data;
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chan->flags = 0;
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#ifndef CONFIG_ARCH_OMAP1
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if (dma_omap2plus()) {
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chan->chain_id = -1;
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chan->next_linked_ch = -1;
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}
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#endif
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chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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if (dma_omap1())
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chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
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else if (dma_omap2plus())
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chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
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OMAP2_DMA_TRANS_ERR_IRQ;
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if (dma_omap16xx()) {
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/* If the sync device is set, configure it dynamically. */
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@ -605,11 +534,6 @@ int omap_request_dma(int dev_id, const char *dev_name,
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p->dma_write(dev_id, CCR, free_ch);
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}
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if (dma_omap2plus()) {
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omap_enable_channel_irq(free_ch);
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omap2_enable_irq_lch(free_ch);
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}
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*dma_ch_out = free_ch;
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return 0;
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@ -626,20 +550,12 @@ void omap_free_dma(int lch)
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return;
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}
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/* Disable interrupt for logical channel */
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if (dma_omap2plus())
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omap2_disable_irq_lch(lch);
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/* Disable all DMA interrupts for the channel. */
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omap_disable_channel_irq(lch);
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/* Make sure the DMA transfer is stopped. */
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p->dma_write(0, CCR, lch);
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/* Clear registers */
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if (dma_omap2plus())
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omap_clear_dma(lch);
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spin_lock_irqsave(&dma_chan_lock, flags);
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dma_chan[lch].dev_id = -1;
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dma_chan[lch].next_lch = -1;
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@ -989,109 +905,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
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#define omap1_dma_irq_handler NULL
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#endif
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#ifdef CONFIG_ARCH_OMAP2PLUS
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static int omap2_dma_handle_ch(int ch)
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{
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u32 status = p->dma_read(CSR, ch);
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if (!status) {
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if (printk_ratelimit())
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pr_warn("Spurious DMA IRQ for lch %d\n", ch);
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p->dma_write(1 << ch, IRQSTATUS_L0, ch);
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return 0;
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}
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if (unlikely(dma_chan[ch].dev_id == -1)) {
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if (printk_ratelimit())
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pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
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status, ch);
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return 0;
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}
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if (unlikely(status & OMAP_DMA_DROP_IRQ))
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pr_info("DMA synchronization event drop occurred with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
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printk(KERN_INFO "DMA transaction error with device %d\n",
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dma_chan[ch].dev_id);
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if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
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u32 ccr;
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ccr = p->dma_read(CCR, ch);
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ccr &= ~OMAP_DMA_CCR_EN;
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p->dma_write(ccr, CCR, ch);
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dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
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}
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}
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if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
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printk(KERN_INFO "DMA secure error with device %d\n",
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dma_chan[ch].dev_id);
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if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
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printk(KERN_INFO "DMA misaligned error with device %d\n",
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dma_chan[ch].dev_id);
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p->dma_write(status, CSR, ch);
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p->dma_write(1 << ch, IRQSTATUS_L0, ch);
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/* read back the register to flush the write */
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p->dma_read(IRQSTATUS_L0, ch);
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/* If the ch is not chained then chain_id will be -1 */
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if (dma_chan[ch].chain_id != -1) {
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int chain_id = dma_chan[ch].chain_id;
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dma_chan[ch].state = DMA_CH_NOTSTARTED;
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if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
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dma_chan[dma_chan[ch].next_linked_ch].state =
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DMA_CH_STARTED;
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if (dma_linked_lch[chain_id].chain_mode ==
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OMAP_DMA_DYNAMIC_CHAIN)
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disable_lnk(ch);
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if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
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OMAP_DMA_CHAIN_INCQHEAD(chain_id);
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status = p->dma_read(CSR, ch);
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p->dma_write(status, CSR, ch);
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}
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if (likely(dma_chan[ch].callback != NULL))
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dma_chan[ch].callback(ch, status, dma_chan[ch].data);
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return 0;
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}
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/* STATUS register count is from 1-32 while our is 0-31 */
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static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
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{
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u32 val, enable_reg;
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int i;
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val = p->dma_read(IRQSTATUS_L0, 0);
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if (val == 0) {
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if (printk_ratelimit())
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printk(KERN_WARNING "Spurious DMA IRQ\n");
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return IRQ_HANDLED;
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}
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enable_reg = p->dma_read(IRQENABLE_L0, 0);
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val &= enable_reg; /* Dispatch only relevant interrupts */
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for (i = 0; i < dma_lch_count && val != 0; i++) {
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if (val & 1)
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omap2_dma_handle_ch(i);
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val >>= 1;
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}
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return IRQ_HANDLED;
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}
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static struct irqaction omap24xx_dma_irq = {
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.name = "DMA",
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.handler = omap2_dma_irq_handler,
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};
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#else
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static struct irqaction omap24xx_dma_irq;
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#endif
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/*----------------------------------------------------------------------------*/
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/*
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* Note that we are currently using only IRQENABLE_L0 and L1.
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* As the DSP may be using IRQENABLE_L2 and L3, let's not
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@ -1139,7 +952,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
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int ch, ret = 0;
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int dma_irq;
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char irq_name[4];
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int irq_rel;
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p = pdev->dev.platform_data;
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if (!p) {
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@ -1165,21 +977,9 @@ static int omap_system_dma_probe(struct platform_device *pdev)
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if (!dma_chan)
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return -ENOMEM;
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if (dma_omap2plus()) {
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dma_linked_lch = kcalloc(dma_lch_count,
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sizeof(*dma_linked_lch),
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GFP_KERNEL);
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if (!dma_linked_lch) {
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ret = -ENOMEM;
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goto exit_dma_lch_fail;
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}
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}
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spin_lock_init(&dma_chan_lock);
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for (ch = 0; ch < dma_chan_count; ch++) {
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omap_clear_dma(ch);
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if (dma_omap2plus())
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omap2_disable_irq_lch(ch);
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dma_chan[ch].dev_id = -1;
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dma_chan[ch].next_lch = -1;
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@ -1216,22 +1016,6 @@ static int omap_system_dma_probe(struct platform_device *pdev)
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omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
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DMA_DEFAULT_FIFO_DEPTH, 0);
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if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
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strcpy(irq_name, "0");
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dma_irq = platform_get_irq_byname(pdev, irq_name);
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if (dma_irq < 0) {
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dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
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ret = dma_irq;
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goto exit_dma_lch_fail;
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}
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ret = setup_irq(dma_irq, &omap24xx_dma_irq);
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if (ret) {
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dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
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dma_irq, ret);
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goto exit_dma_lch_fail;
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}
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}
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/* reserve dma channels 0 and 1 in high security devices on 34xx */
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if (d->dev_caps & HS_CHANNELS_RESERVED) {
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pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
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@ -1242,34 +1026,21 @@ static int omap_system_dma_probe(struct platform_device *pdev)
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return 0;
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exit_dma_irq_fail:
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dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
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dma_irq, ret);
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for (irq_rel = 0; irq_rel < ch; irq_rel++) {
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dma_irq = platform_get_irq(pdev, irq_rel);
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free_irq(dma_irq, (void *)(irq_rel + 1));
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}
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exit_dma_lch_fail:
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return ret;
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}
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static int omap_system_dma_remove(struct platform_device *pdev)
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{
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int dma_irq;
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int dma_irq, irq_rel = 0;
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if (dma_omap2plus()) {
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char irq_name[4];
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strcpy(irq_name, "0");
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dma_irq = platform_get_irq_byname(pdev, irq_name);
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if (dma_irq >= 0)
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remove_irq(dma_irq, &omap24xx_dma_irq);
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} else {
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int irq_rel = 0;
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for ( ; irq_rel < dma_chan_count; irq_rel++) {
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dma_irq = platform_get_irq(pdev, irq_rel);
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free_irq(dma_irq, (void *)(irq_rel + 1));
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}
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if (dma_omap2plus())
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return 0;
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for ( ; irq_rel < dma_chan_count; irq_rel++) {
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dma_irq = platform_get_irq(pdev, irq_rel);
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free_irq(dma_irq, (void *)(irq_rel + 1));
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}
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return 0;
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}
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@ -129,7 +129,6 @@
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#define IS_WORD_16 BIT(0xd)
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#define ENABLE_16XX_MODE BIT(0xe)
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#define HS_CHANNELS_RESERVED BIT(0xf)
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#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
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/* Defines for DMA Capabilities */
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#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
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@ -239,9 +238,6 @@ struct omap_dma_lch {
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void (*callback)(int lch, u16 ch_status, void *data);
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void *data;
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long flags;
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/* required for Dynamic chaining */
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int prev_linked_ch;
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int next_linked_ch;
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int state;
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int chain_id;
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int status;
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