Amlogic 64-bit DT updates for v4.16, round 2
- clock, pinctrl, PWM and reset nodes for new AXG SoC family -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlpL5v0ACgkQWTcYmtP7 xmWJHg//SBn8YMMm7DISpiemotfeX3VtKsPpvZwmbjQI4TuercobVk8Kl9IA/mzi BNREL5u/mvYk7HnClq3wQzl/S8eCF2y4pBHkO3z0LuP6oEqa53HwfrDv8Gw+fJDd +ovx65AKHjfTadqtFPp5ZTJBZOC50HJCHpCzKAaHeEiiQgMGNDkJqtM3gP9s+4yx 6Ny7gdO8oapVxOLxq5riyQHqjjPRrS+UX3pmhguTrJsnISGQGGGRH5UH4vetWs61 ZEKk0AhngQC/nNfrFY9Rdlx3hV1LdrmIC6DJttMETY/YkxgMgz76XL/1URB+/fFg SEm6MaFQusIWdpkMWcb0slzWdIo5u8LayXT0p8CkimeKeo/fdDhMtiamFKsRdWi8 k4870UZO2LZNZ7aiaZZYUnRR1ksQ9uHCuUKcETW82pIvS/rnTUUkCnmzHTGgXHDZ 7AWkGK7YM6CoKF7UOhfWaK5wpORNuKiD5kJFxR49EHcB29Zb1ls4mOQwtdM6DEHK Hb5xv/1HekQytNouhkkxPFEB6+sWixTY96vsWtFI9cvcmoH/OLACgYOwlkjyxsY5 9fNhCzD/5FBVvYLmiREdlVc5TztsxO3iZNMEBmPg97et+J/3eHoNjmTSKt0e/CCR pFBnBx4AKeZwcegZcBZV5LzFUvncT6Ucpc9UNBoXHHF0jbrnUc4= =4k+i -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 64-bit DT updates for v4.16, round 2" from Kevin Hilman: This adds a few more basics (clock, pinctrl, PWM, reset) for the new AXG family of Amlogic SoCs. * tag 'amlogic-dt64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-axg: add new reset DT node ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC documentation: Add compatibles for Amlogic Meson AXG pin controllers arm64: dts: meson-axg: add clock DT info for Meson AXG SoC
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commit
7598a4e035
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@ -9,6 +9,8 @@ Required properties for the root node:
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"amlogic,meson-gxbb-aobus-pinctrl"
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"amlogic,meson-gxl-periphs-pinctrl"
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"amlogic,meson-gxl-aobus-pinctrl"
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"amlogic,meson-axg-periphs-pinctrl"
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"amlogic,meson-axg-aobus-pinctrl"
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- reg: address and size of registers controlling irq functionality
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=== GPIO sub-nodes ===
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@ -120,6 +120,26 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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pwm_ab: pwm@1b000 {
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compatible = "amlogic,meson-axg-ee-pwm";
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reg = <0x0 0x1b000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_cd: pwm@1a000 {
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compatible = "amlogic,meson-axg-ee-pwm";
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reg = <0x0 0x1a000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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reset: reset-controller@1004 {
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compatible = "amlogic,meson-axg-reset";
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reg = <0x0 0x01004 0x0 0x9c>;
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#reset-cells = <1>;
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};
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uart_A: serial@24000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x24000 0x0 0x14>;
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@ -148,6 +168,20 @@
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#address-cells = <0>;
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};
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hiubus: bus@ff63c000 {
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compatible = "simple-bus";
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reg = <0x0 0xff63c000 0x0 0x1c00>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
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clkc: clock-controller@0 {
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compatible = "amlogic,axg-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x320>;
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};
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};
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mailbox: mailbox@ff63dc00 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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reg = <0 0xff63dc00 0 0x400>;
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@ -157,6 +191,116 @@
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#mbox-cells = <1>;
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};
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periphs: periphs@ff634000 {
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compatible = "simple-bus";
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reg = <0x0 0xff634000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
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pinctrl_periphs: pinctrl@480 {
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compatible = "amlogic,meson-axg-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@480 {
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reg = <0x0 0x00480 0x0 0x40>,
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<0x0 0x004e8 0x0 0x14>,
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<0x0 0x00520 0x0 0x14>,
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<0x0 0x00430 0x0 0x3c>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 0 86>;
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};
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pwm_a_a_pins: pwm_a_a {
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mux {
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groups = "pwm_a_a";
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function = "pwm_a";
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};
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};
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pwm_a_x18_pins: pwm_a_x18 {
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mux {
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groups = "pwm_a_x18";
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function = "pwm_a";
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};
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};
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pwm_a_x20_pins: pwm_a_x20 {
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mux {
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groups = "pwm_a_x20";
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function = "pwm_a";
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};
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};
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pwm_a_z_pins: pwm_a_z {
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mux {
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groups = "pwm_a_z";
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function = "pwm_a";
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};
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};
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pwm_b_a_pins: pwm_b_a {
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mux {
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groups = "pwm_b_a";
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function = "pwm_b";
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};
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};
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pwm_b_x_pins: pwm_b_x {
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mux {
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groups = "pwm_b_x";
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function = "pwm_b";
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};
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};
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pwm_b_z_pins: pwm_b_z {
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mux {
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groups = "pwm_b_z";
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function = "pwm_b";
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};
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};
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pwm_c_a_pins: pwm_c_a {
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mux {
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groups = "pwm_c_a";
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function = "pwm_c";
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};
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};
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pwm_c_x10_pins: pwm_c_x10 {
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mux {
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groups = "pwm_c_x10";
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function = "pwm_c";
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};
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};
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pwm_c_x17_pins: pwm_c_x17 {
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mux {
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groups = "pwm_c_x17";
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function = "pwm_c";
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};
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};
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pwm_d_x11_pins: pwm_d_x11 {
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mux {
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groups = "pwm_d_x11";
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function = "pwm_d";
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};
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};
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pwm_d_x16_pins: pwm_d_x16 {
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mux {
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groups = "pwm_d_x16";
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function = "pwm_d";
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};
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};
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};
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};
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sram: sram@fffc0000 {
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compatible = "amlogic,meson-axg-sram", "mmio-sram";
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reg = <0x0 0xfffc0000 0x0 0x20000>;
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@ -182,6 +326,37 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-axg-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@14 {
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reg = <0x0 0x00014 0x0 0x8>,
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<0x0 0x0002c 0x0 0x4>,
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<0x0 0x00024 0x0 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 15>;
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};
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};
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pwm_AO_ab: pwm@7000 {
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compatible = "amlogic,meson-axg-ao-pwm";
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reg = <0x0 0x07000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_AO_cd: pwm@2000 {
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compatible = "amlogic,axg-ao-pwm";
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reg = <0x0 0x02000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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