i2c: rcar: Revert the latest refactoring series
This whole series caused sometimes timeouts and even OOPSes on some r8a7791 Koelsch boards. We need to understand and fix those first. Revert "i2c: rcar: clean up after refactoring" Revert "i2c: rcar: revoke START request early" Revert "i2c: rcar: check master irqs before slave irqs" Revert "i2c: rcar: don't issue stop when HW does it automatically" Revert "i2c: rcar: init new messages in irq" Revert "i2c: rcar: refactor setup of a msg" Revert "i2c: rcar: remove spinlock" Revert "i2c: rcar: remove unused IOERROR state" Revert "i2c: rcar: rework hw init" Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Wolfram Sang
Wolfram Sang
parent
77133e1c03
commit
75ecc64ef5
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@ -1,8 +1,7 @@
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/*
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* Driver for the Renesas RCar I2C unit
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*
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* Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
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* Copyright (C) 2011-2015 Renesas Electronics Corporation
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* Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
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*
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* Copyright (C) 2012-14 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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@ -10,6 +9,9 @@
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* This file is based on the drivers/i2c/busses/i2c-sh7760.c
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* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
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*
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* This file used out-of-tree driver i2c-rcar.c
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* Copyright (C) 2011-2012 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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@ -31,6 +33,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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/* register offsets */
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#define ICSCR 0x00 /* slave ctrl */
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@ -81,7 +84,6 @@
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#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
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#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
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#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
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#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
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#define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
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@ -92,6 +94,7 @@
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#define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
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#define ID_LAST_MSG (1 << 0)
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#define ID_IOERROR (1 << 1)
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#define ID_DONE (1 << 2)
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#define ID_ARBLOST (1 << 3)
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#define ID_NACK (1 << 4)
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@ -105,10 +108,10 @@ enum rcar_i2c_type {
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struct rcar_i2c_priv {
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void __iomem *io;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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int msgs_left;
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struct i2c_msg *msg;
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struct clk *clk;
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spinlock_t lock;
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wait_queue_head_t wait;
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int pos;
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@ -141,10 +144,9 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
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{
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/* reset master mode */
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rcar_i2c_write(priv, ICMIER, 0);
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rcar_i2c_write(priv, ICMCR, MDBS);
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rcar_i2c_write(priv, ICMCR, 0);
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rcar_i2c_write(priv, ICMSR, 0);
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/* start clock */
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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rcar_i2c_write(priv, ICMAR, 0);
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}
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static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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@ -243,7 +245,9 @@ scgd_find:
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dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
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scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
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/* keep icccr value */
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/*
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* keep icccr value
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*/
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priv->icccr = scgd << cdf_width | cdf;
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return 0;
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@ -253,24 +257,12 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
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{
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int read = !!rcar_i2c_is_recv(priv);
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priv->pos = 0;
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priv->flags = 0;
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if (priv->msgs_left == 1)
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rcar_i2c_flags_set(priv, ID_LAST_MSG);
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rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
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rcar_i2c_write(priv, ICMSR, 0);
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
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rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
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}
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static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
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{
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priv->msg++;
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priv->msgs_left--;
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rcar_i2c_prepare_msg(priv);
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}
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/*
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* interrupt functions
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*/
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@ -278,10 +270,21 @@ static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/* FIXME: sometimes, unknown interrupt happened. Do nothing */
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDE))
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return 0;
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/*
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* If address transfer phase finished,
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* goto data phase.
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*/
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if (msr & MAT)
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
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if (priv->pos < msg->len) {
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/*
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* Prepare next data to ICRXTX register.
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@ -302,17 +305,21 @@ static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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if (priv->flags & ID_LAST_MSG) {
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if (priv->flags & ID_LAST_MSG)
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/*
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* If current msg is the _LAST_ msg,
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* prepare stop condition here.
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* ID_DONE will be set on STOP irq.
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*/
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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} else {
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rcar_i2c_next_msg(priv);
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return 0;
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}
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else
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/*
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* If current msg is _NOT_ last msg,
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* it doesn't call stop phase.
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* thus, there is no STOP irq.
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* return ID_DONE here.
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*/
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return ID_DONE;
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}
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
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@ -324,30 +331,39 @@ static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/* FIXME: sometimes, unknown interrupt happened. Do nothing */
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDR))
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return 0;
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if (msr & MAT) {
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/* Address transfer phase finished, but no data at this point. */
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/*
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* Address transfer phase finished,
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* but, there is no data at this point.
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* Do nothing.
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*/
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} else if (priv->pos < msg->len) {
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/* get received data */
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/*
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* get received data
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*/
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msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
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priv->pos++;
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}
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/*
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* If next received data is the _LAST_, go to STOP phase. Might be
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* overwritten by REP START when setting up a new msg. Not elegant
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* but the only stable sequence for REP START I have found so far.
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* If next received data is the _LAST_,
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* go to STOP phase,
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* otherwise, go to DATA phase.
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*/
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if (priv->pos + 1 >= msg->len)
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
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rcar_i2c_next_msg(priv);
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else
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
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return 0;
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}
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@ -410,21 +426,22 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
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static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
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{
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struct rcar_i2c_priv *priv = ptr;
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u32 msr, val;
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irqreturn_t result = IRQ_HANDLED;
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u32 msr;
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/* Clear START or STOP as soon as we can */
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val = rcar_i2c_read(priv, ICMCR);
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rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
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/*-------------- spin lock -----------------*/
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spin_lock(&priv->lock);
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if (rcar_i2c_slave_irq(priv))
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goto exit;
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msr = rcar_i2c_read(priv, ICMSR);
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/* Only handle interrupts that are currently enabled */
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msr &= rcar_i2c_read(priv, ICMIER);
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if (!msr) {
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if (rcar_i2c_slave_irq(priv))
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return IRQ_HANDLED;
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return IRQ_NONE;
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result = IRQ_NONE;
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goto exit;
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}
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/* Arbitration lost */
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@ -435,7 +452,8 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
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/* Nack */
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if (msr & MNR) {
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/* HW automatically sends STOP after received NACK */
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/* go to stop phase */
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
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rcar_i2c_flags_set(priv, ID_NACK);
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goto out;
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@ -443,7 +461,6 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
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/* Stop */
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if (msr & MST) {
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priv->msgs_left--; /* The last message also made it */
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rcar_i2c_flags_set(priv, ID_DONE);
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goto out;
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}
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@ -460,7 +477,11 @@ out:
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wake_up(&priv->wait);
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}
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return IRQ_HANDLED;
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exit:
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spin_unlock(&priv->lock);
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/*-------------- spin unlock -----------------*/
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return result;
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}
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static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
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@ -469,11 +490,22 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
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{
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struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
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struct device *dev = rcar_i2c_priv_to_dev(priv);
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unsigned long flags;
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int i, ret;
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long time_left;
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long timeout;
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pm_runtime_get_sync(dev);
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/*-------------- spin lock -----------------*/
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spin_lock_irqsave(&priv->lock, flags);
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rcar_i2c_init(priv);
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/* start clock */
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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spin_unlock_irqrestore(&priv->lock, flags);
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/*-------------- spin unlock -----------------*/
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ret = rcar_i2c_bus_barrier(priv);
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if (ret < 0)
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goto out;
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@ -482,28 +514,48 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
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/* This HW can't send STOP after address phase */
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if (msgs[i].len == 0) {
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ret = -EOPNOTSUPP;
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goto out;
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break;
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}
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}
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/* init data */
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priv->msg = msgs;
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priv->msgs_left = num;
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/*-------------- spin lock -----------------*/
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spin_lock_irqsave(&priv->lock, flags);
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rcar_i2c_prepare_msg(priv);
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/* init each data */
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priv->msg = &msgs[i];
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priv->pos = 0;
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priv->flags = 0;
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if (i == num - 1)
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rcar_i2c_flags_set(priv, ID_LAST_MSG);
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time_left = wait_event_timeout(priv->wait,
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rcar_i2c_flags_has(priv, ID_DONE),
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num * adap->timeout);
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if (!time_left) {
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rcar_i2c_init(priv);
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ret = -ETIMEDOUT;
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} else if (rcar_i2c_flags_has(priv, ID_NACK)) {
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ret = -ENXIO;
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} else if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
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ret = -EAGAIN;
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} else {
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ret = num - priv->msgs_left; /* The number of transfer */
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rcar_i2c_prepare_msg(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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/*-------------- spin unlock -----------------*/
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timeout = wait_event_timeout(priv->wait,
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rcar_i2c_flags_has(priv, ID_DONE),
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adap->timeout);
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if (!timeout) {
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ret = -ETIMEDOUT;
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break;
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}
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if (rcar_i2c_flags_has(priv, ID_NACK)) {
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ret = -ENXIO;
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break;
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}
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if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
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ret = -EAGAIN;
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break;
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}
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if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
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ret = -EIO;
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break;
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}
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ret = i + 1; /* The number of transfer */
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}
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out:
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pm_runtime_put(dev);
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@ -612,10 +664,9 @@ static int rcar_i2c_probe(struct platform_device *pdev)
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if (IS_ERR(priv->io))
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return PTR_ERR(priv->io);
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rcar_i2c_init(priv);
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irq = platform_get_irq(pdev, 0);
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init_waitqueue_head(&priv->wait);
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spin_lock_init(&priv->lock);
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adap = &priv->adap;
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adap->nr = pdev->id;
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