xhci: Features for 3.12
In the spirit of "let's stop gossiping around the water cooler and get to work", here's some xHCI patches for 3.12. They include a patch for suspend/resume support for xhci platform hosts, two patches to support showing USB 2.1 link status, and a patch to future-proof the Intel EHCI to xHCI port switchover. Sarah Sharp -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJR7vxeAAoJEBMGWMLi1Gc56VoQAI9RwDPAjx5aqj2Gg1uAZmh6 x965vdIjrEd+ND5rLS/G1khkTWW7o0SW2rwwuGhMOsrPve6R+Dr+rXoFxvPSpyTZ 1F+eiSNX+lmPtbeSrdNo5u+787yNR0UuvfDP5uIrqcrA3lo6Xc5Sk3qQ7fqEd9rg iSAQ7WwAKgpO40QMOFwTLi257mDfGJPg5d8cwwa9OAe3a7DVFHYfxv1vxmDFlR/w KPgq38hjR5S8Npcl9mC2RpjQoj1e3oO+4kZJX2CPmrRWx7GWAGfg/alDSGzl3zwk A8juRlKQGiFb9LmFwtvtHqolJuBGtTdSj0jPe1MObCw6LWzQcF2RppnTFlt/JHxp mpBRG94QC0ssHkUFhBKIlQLpL1KQiyUiWsBUyjaxtiVUMzZSt482Wnhnwr5lr1sn /WHnVY5MeWuAyFVx79+2KgRRbEaL0OnEGqEaIf/tfZL7D7dbDMkcOsOALguAvI4a 33KKSeiIyNqWcRXhQ9lVVxlsfS6ZFHl9MZvqIbhfO3Uzd4HIW+EdXOo2zx7GIlUO Zds5bpiV8wpDXzVHkY6NMr8HJWrD7pmD22o8tm8wY+LzO4Vxjdyxbvi5waSfPzYv 5FGVd9qN9tAif0xlhDj7GN63cF0rjgoFfBkfZcP+Y0Tvk2Po9mobzLoQwerDI7uJ v5BIoDuGBaDWIycJMYO2 =K3xk -----END PGP SIGNATURE----- Merge tag 'for-usb-next-2013-07-23' of git://git.kernel.org/pub/scm/linux/kernel/git/sarah/xhci into usb-next Sarah writes: xhci: Features for 3.12 In the spirit of "let's stop gossiping around the water cooler and get to work", here's some xHCI patches for 3.12. They include a patch for suspend/resume support for xhci platform hosts, two patches to support showing USB 2.1 link status, and a patch to future-proof the Intel EHCI to xHCI port switchover. Sarah Sharp
This commit is contained in:
commit
7603dee3bd
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@ -315,53 +315,11 @@ done:
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* Also they depend on separate root hub suspend/resume.
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*/
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static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
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{
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return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
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pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == 0x1E26 ||
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pdev->device == 0x8C2D ||
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pdev->device == 0x8C26 ||
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pdev->device == 0x9C26);
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}
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static void ehci_enable_xhci_companion(void)
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{
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struct pci_dev *companion = NULL;
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/* The xHCI and EHCI controllers are not on the same PCI slot */
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for_each_pci_dev(companion) {
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if (!usb_is_intel_switchable_xhci(companion))
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continue;
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usb_enable_xhci_ports(companion);
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return;
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}
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}
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static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/* The BIOS on systems with the Intel Panther Point chipset may or may
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* not support xHCI natively. That means that during system resume, it
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* may switch the ports back to EHCI so that users can use their
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* keyboard to select a kernel from GRUB after resume from hibernate.
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*
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* The BIOS is supposed to remember whether the OS had xHCI ports
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* enabled before resume, and switch the ports back to xHCI when the
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* BIOS/OS semaphore is written, but we all know we can't trust BIOS
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* writers.
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*
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* Unconditionally switch the ports back to xHCI after a system resume.
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* We can't tell whether the EHCI or xHCI controller will be resumed
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* first, so we have to do the port switchover in both drivers. Writing
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* a '1' to the port switchover registers should have no effect if the
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* port was already switched over.
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*/
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if (usb_is_intel_switchable_ehci(pdev))
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ehci_enable_xhci_companion();
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if (ehci_resume(hcd, hibernated) != 0)
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(void) ehci_pci_reinit(ehci, pdev);
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return 0;
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@ -735,32 +735,6 @@ static int handshake(void __iomem *ptr, u32 mask, u32 done,
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return -ETIMEDOUT;
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}
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#define PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI 0x8C31
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#define PCI_DEVICE_ID_INTEL_LYNX_POINT_LP_XHCI 0x9C31
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bool usb_is_intel_ppt_switchable_xhci(struct pci_dev *pdev)
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{
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return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
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pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
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}
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/* The Intel Lynx Point chipset also has switchable ports. */
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bool usb_is_intel_lpt_switchable_xhci(struct pci_dev *pdev)
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{
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return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
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pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_LYNX_POINT_LP_XHCI);
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}
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bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
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{
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return usb_is_intel_ppt_switchable_xhci(pdev) ||
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usb_is_intel_lpt_switchable_xhci(pdev);
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}
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EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
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/*
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* Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
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* share some number of ports. These ports can be switched between either
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@ -779,9 +753,23 @@ EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
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* terminations before switching the USB 2.0 wires over, so that USB 3.0
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* devices connect at SuperSpeed, rather than at USB 2.0 speeds.
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*/
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void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
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void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
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{
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u32 ports_available;
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bool ehci_found = false;
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struct pci_dev *companion = NULL;
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/* make sure an intel EHCI controller exists */
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for_each_pci_dev(companion) {
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if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
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companion->vendor == PCI_VENDOR_ID_INTEL) {
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ehci_found = true;
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break;
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}
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}
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if (!ehci_found)
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return;
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/* Don't switchover the ports if the user hasn't compiled the xHCI
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* driver. Otherwise they will see "dead" USB ports that don't power
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@ -840,7 +828,7 @@ void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
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dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
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"to xHCI: 0x%x\n", ports_available);
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}
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EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
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EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
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void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
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{
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@ -921,8 +909,8 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
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writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
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hc_init:
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if (usb_is_intel_switchable_xhci(pdev))
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usb_enable_xhci_ports(pdev);
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if (pdev->vendor == PCI_VENDOR_ID_INTEL)
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usb_enable_intel_xhci_ports(pdev);
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op_reg_base = base + XHCI_HC_LENGTH(readl(base));
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@ -8,8 +8,7 @@ int usb_amd_find_chipset_info(void);
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void usb_amd_dev_put(void);
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void usb_amd_quirk_pll_disable(void);
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void usb_amd_quirk_pll_enable(void);
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bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
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void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
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void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev);
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void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
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void sb800_prefetch(struct device *dev, int on);
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#else
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@ -461,8 +461,15 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
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}
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}
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/* Updates Link Status for USB 2.1 port */
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static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
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{
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if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
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*status |= USB_PORT_STAT_L1;
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}
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/* Updates Link Status for super Speed port */
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static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
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static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
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{
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u32 pls = status_reg & PORT_PLS_MASK;
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@ -534,6 +541,120 @@ void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
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}
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}
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/*
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* Converts a raw xHCI port status into the format that external USB 2.0 or USB
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* 3.0 hubs use.
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*
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* Possible side effects:
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* - Mark a port as being done with device resume,
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* and ring the endpoint doorbells.
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* - Stop the Synopsys redriver Compliance Mode polling.
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*/
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static u32 xhci_get_port_status(struct usb_hcd *hcd,
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struct xhci_bus_state *bus_state,
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__le32 __iomem **port_array,
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u16 wIndex, u32 raw_port_status)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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u32 status = 0;
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int slot_id;
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/* wPortChange bits */
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if (raw_port_status & PORT_CSC)
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status |= USB_PORT_STAT_C_CONNECTION << 16;
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if (raw_port_status & PORT_PEC)
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status |= USB_PORT_STAT_C_ENABLE << 16;
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if ((raw_port_status & PORT_OCC))
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status |= USB_PORT_STAT_C_OVERCURRENT << 16;
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if ((raw_port_status & PORT_RC))
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status |= USB_PORT_STAT_C_RESET << 16;
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/* USB3.0 only */
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if (hcd->speed == HCD_USB3) {
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if ((raw_port_status & PORT_PLC))
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status |= USB_PORT_STAT_C_LINK_STATE << 16;
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if ((raw_port_status & PORT_WRC))
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status |= USB_PORT_STAT_C_BH_RESET << 16;
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}
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if (hcd->speed != HCD_USB3) {
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if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
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&& (raw_port_status & PORT_POWER))
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status |= USB_PORT_STAT_SUSPEND;
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}
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if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
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!DEV_SUPERSPEED(raw_port_status)) {
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if ((raw_port_status & PORT_RESET) ||
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!(raw_port_status & PORT_PE))
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return 0xffffffff;
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if (time_after_eq(jiffies,
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bus_state->resume_done[wIndex])) {
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xhci_dbg(xhci, "Resume USB2 port %d\n",
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wIndex + 1);
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bus_state->resume_done[wIndex] = 0;
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clear_bit(wIndex, &bus_state->resuming_ports);
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xhci_set_link_state(xhci, port_array, wIndex,
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XDEV_U0);
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xhci_dbg(xhci, "set port %d resume\n",
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wIndex + 1);
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slot_id = xhci_find_slot_id_by_port(hcd, xhci,
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wIndex + 1);
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if (!slot_id) {
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xhci_dbg(xhci, "slot_id is zero\n");
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return 0xffffffff;
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}
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xhci_ring_device(xhci, slot_id);
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bus_state->port_c_suspend |= 1 << wIndex;
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bus_state->suspended_ports &= ~(1 << wIndex);
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} else {
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/*
|
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* The resume has been signaling for less than
|
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* 20ms. Report the port status as SUSPEND,
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* let the usbcore check port status again
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* and clear resume signaling later.
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*/
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status |= USB_PORT_STAT_SUSPEND;
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}
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}
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if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
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&& (raw_port_status & PORT_POWER)
|
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&& (bus_state->suspended_ports & (1 << wIndex))) {
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bus_state->suspended_ports &= ~(1 << wIndex);
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if (hcd->speed != HCD_USB3)
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bus_state->port_c_suspend |= 1 << wIndex;
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}
|
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if (raw_port_status & PORT_CONNECT) {
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status |= USB_PORT_STAT_CONNECTION;
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status |= xhci_port_speed(raw_port_status);
|
||||
}
|
||||
if (raw_port_status & PORT_PE)
|
||||
status |= USB_PORT_STAT_ENABLE;
|
||||
if (raw_port_status & PORT_OC)
|
||||
status |= USB_PORT_STAT_OVERCURRENT;
|
||||
if (raw_port_status & PORT_RESET)
|
||||
status |= USB_PORT_STAT_RESET;
|
||||
if (raw_port_status & PORT_POWER) {
|
||||
if (hcd->speed == HCD_USB3)
|
||||
status |= USB_SS_PORT_STAT_POWER;
|
||||
else
|
||||
status |= USB_PORT_STAT_POWER;
|
||||
}
|
||||
/* Update Port Link State */
|
||||
if (hcd->speed == HCD_USB3) {
|
||||
xhci_hub_report_usb3_link_state(&status, raw_port_status);
|
||||
/*
|
||||
* Verify if all USB3 Ports Have entered U0 already.
|
||||
* Delete Compliance Mode Timer if so.
|
||||
*/
|
||||
xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
|
||||
} else {
|
||||
xhci_hub_report_usb2_link_state(&status, raw_port_status);
|
||||
}
|
||||
if (bus_state->port_c_suspend & (1 << wIndex))
|
||||
status |= 1 << USB_PORT_FEAT_C_SUSPEND;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
|
||||
u16 wIndex, char *buf, u16 wLength)
|
||||
{
|
||||
|
@ -598,104 +719,20 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
|
|||
if (!wIndex || wIndex > max_ports)
|
||||
goto error;
|
||||
wIndex--;
|
||||
status = 0;
|
||||
temp = xhci_readl(xhci, port_array[wIndex]);
|
||||
if (temp == 0xffffffff) {
|
||||
retval = -ENODEV;
|
||||
break;
|
||||
}
|
||||
xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
|
||||
status = xhci_get_port_status(hcd, bus_state, port_array,
|
||||
wIndex, temp);
|
||||
if (status == 0xffffffff)
|
||||
goto error;
|
||||
|
||||
/* wPortChange bits */
|
||||
if (temp & PORT_CSC)
|
||||
status |= USB_PORT_STAT_C_CONNECTION << 16;
|
||||
if (temp & PORT_PEC)
|
||||
status |= USB_PORT_STAT_C_ENABLE << 16;
|
||||
if ((temp & PORT_OCC))
|
||||
status |= USB_PORT_STAT_C_OVERCURRENT << 16;
|
||||
if ((temp & PORT_RC))
|
||||
status |= USB_PORT_STAT_C_RESET << 16;
|
||||
/* USB3.0 only */
|
||||
if (hcd->speed == HCD_USB3) {
|
||||
if ((temp & PORT_PLC))
|
||||
status |= USB_PORT_STAT_C_LINK_STATE << 16;
|
||||
if ((temp & PORT_WRC))
|
||||
status |= USB_PORT_STAT_C_BH_RESET << 16;
|
||||
}
|
||||
|
||||
if (hcd->speed != HCD_USB3) {
|
||||
if ((temp & PORT_PLS_MASK) == XDEV_U3
|
||||
&& (temp & PORT_POWER))
|
||||
status |= USB_PORT_STAT_SUSPEND;
|
||||
}
|
||||
if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
|
||||
!DEV_SUPERSPEED(temp)) {
|
||||
if ((temp & PORT_RESET) || !(temp & PORT_PE))
|
||||
goto error;
|
||||
if (time_after_eq(jiffies,
|
||||
bus_state->resume_done[wIndex])) {
|
||||
xhci_dbg(xhci, "Resume USB2 port %d\n",
|
||||
wIndex + 1);
|
||||
bus_state->resume_done[wIndex] = 0;
|
||||
clear_bit(wIndex, &bus_state->resuming_ports);
|
||||
xhci_set_link_state(xhci, port_array, wIndex,
|
||||
XDEV_U0);
|
||||
xhci_dbg(xhci, "set port %d resume\n",
|
||||
wIndex + 1);
|
||||
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
|
||||
wIndex + 1);
|
||||
if (!slot_id) {
|
||||
xhci_dbg(xhci, "slot_id is zero\n");
|
||||
goto error;
|
||||
}
|
||||
xhci_ring_device(xhci, slot_id);
|
||||
bus_state->port_c_suspend |= 1 << wIndex;
|
||||
bus_state->suspended_ports &= ~(1 << wIndex);
|
||||
} else {
|
||||
/*
|
||||
* The resume has been signaling for less than
|
||||
* 20ms. Report the port status as SUSPEND,
|
||||
* let the usbcore check port status again
|
||||
* and clear resume signaling later.
|
||||
*/
|
||||
status |= USB_PORT_STAT_SUSPEND;
|
||||
}
|
||||
}
|
||||
if ((temp & PORT_PLS_MASK) == XDEV_U0
|
||||
&& (temp & PORT_POWER)
|
||||
&& (bus_state->suspended_ports & (1 << wIndex))) {
|
||||
bus_state->suspended_ports &= ~(1 << wIndex);
|
||||
if (hcd->speed != HCD_USB3)
|
||||
bus_state->port_c_suspend |= 1 << wIndex;
|
||||
}
|
||||
if (temp & PORT_CONNECT) {
|
||||
status |= USB_PORT_STAT_CONNECTION;
|
||||
status |= xhci_port_speed(temp);
|
||||
}
|
||||
if (temp & PORT_PE)
|
||||
status |= USB_PORT_STAT_ENABLE;
|
||||
if (temp & PORT_OC)
|
||||
status |= USB_PORT_STAT_OVERCURRENT;
|
||||
if (temp & PORT_RESET)
|
||||
status |= USB_PORT_STAT_RESET;
|
||||
if (temp & PORT_POWER) {
|
||||
if (hcd->speed == HCD_USB3)
|
||||
status |= USB_SS_PORT_STAT_POWER;
|
||||
else
|
||||
status |= USB_PORT_STAT_POWER;
|
||||
}
|
||||
/* Update Port Link State for super speed ports*/
|
||||
if (hcd->speed == HCD_USB3) {
|
||||
xhci_hub_report_link_state(&status, temp);
|
||||
/*
|
||||
* Verify if all USB3 Ports Have entered U0 already.
|
||||
* Delete Compliance Mode Timer if so.
|
||||
*/
|
||||
xhci_del_comp_mod_timer(xhci, temp, wIndex);
|
||||
}
|
||||
if (bus_state->port_c_suspend & (1 << wIndex))
|
||||
status |= 1 << USB_PORT_FEAT_C_SUSPEND;
|
||||
xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
|
||||
wIndex, temp);
|
||||
xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
|
||||
|
||||
put_unaligned(cpu_to_le32(status), (__le32 *) buf);
|
||||
break;
|
||||
case SetPortFeature:
|
||||
|
|
|
@ -250,13 +250,15 @@ static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
|
|||
* writers.
|
||||
*
|
||||
* Unconditionally switch the ports back to xHCI after a system resume.
|
||||
* We can't tell whether the EHCI or xHCI controller will be resumed
|
||||
* first, so we have to do the port switchover in both drivers. Writing
|
||||
* a '1' to the port switchover registers should have no effect if the
|
||||
* port was already switched over.
|
||||
* It should not matter whether the EHCI or xHCI controller is
|
||||
* resumed first. It's enough to do the switchover in xHCI because
|
||||
* USB core won't notice anything as the hub driver doesn't start
|
||||
* running again until after all the devices (including both EHCI and
|
||||
* xHCI host controllers) have been resumed.
|
||||
*/
|
||||
if (usb_is_intel_switchable_xhci(pdev))
|
||||
usb_enable_xhci_ports(pdev);
|
||||
|
||||
if (pdev->vendor == PCI_VENDOR_ID_INTEL)
|
||||
usb_enable_intel_xhci_ports(pdev);
|
||||
|
||||
retval = xhci_resume(xhci, hibernated);
|
||||
return retval;
|
||||
|
|
|
@ -186,11 +186,37 @@ static int xhci_plat_remove(struct platform_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int xhci_plat_suspend(struct device *dev)
|
||||
{
|
||||
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
||||
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
||||
|
||||
return xhci_suspend(xhci);
|
||||
}
|
||||
|
||||
static int xhci_plat_resume(struct device *dev)
|
||||
{
|
||||
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
||||
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
||||
|
||||
return xhci_resume(xhci, 0);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops xhci_plat_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(xhci_plat_suspend, xhci_plat_resume)
|
||||
};
|
||||
#define DEV_PM_OPS (&xhci_plat_pm_ops)
|
||||
#else
|
||||
#define DEV_PM_OPS NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct platform_driver usb_xhci_driver = {
|
||||
.probe = xhci_plat_probe,
|
||||
.remove = xhci_plat_remove,
|
||||
.driver = {
|
||||
.name = "xhci-hcd",
|
||||
.pm = DEV_PM_OPS,
|
||||
},
|
||||
};
|
||||
MODULE_ALIAS("platform:xhci-hcd");
|
||||
|
|
|
@ -3075,8 +3075,8 @@ static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
|
|||
/* Are streams already being freed for the endpoint? */
|
||||
if (ep_state & EP_GETTING_NO_STREAMS) {
|
||||
xhci_warn(xhci, "WARN Can't disable streams for "
|
||||
"endpoint 0x%x\n, "
|
||||
"streams are being disabled already.",
|
||||
"endpoint 0x%x, "
|
||||
"streams are being disabled already\n",
|
||||
eps[i]->desc.bEndpointAddress);
|
||||
return 0;
|
||||
}
|
||||
|
@ -3084,8 +3084,8 @@ static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
|
|||
if (!(ep_state & EP_HAS_STREAMS) &&
|
||||
!(ep_state & EP_GETTING_STREAMS)) {
|
||||
xhci_warn(xhci, "WARN Can't disable streams for "
|
||||
"endpoint 0x%x\n, "
|
||||
"streams are already disabled!",
|
||||
"endpoint 0x%x, "
|
||||
"streams are already disabled!\n",
|
||||
eps[i]->desc.bEndpointAddress);
|
||||
xhci_warn(xhci, "WARN xhci_free_streams() called "
|
||||
"with non-streams endpoint\n");
|
||||
|
@ -4353,7 +4353,7 @@ static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
|
|||
state_name, sel);
|
||||
else
|
||||
dev_dbg(&udev->dev, "Device-initiated %s disabled "
|
||||
"due to long PEL %llu\n ms",
|
||||
"due to long PEL %llu ms\n",
|
||||
state_name, pel);
|
||||
return USB3_LPM_DISABLED;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue