Merge remote-tracking branch 'wireless-next/master' into mac80211-next
This brings in some mwifiex changes that further patches will need to work on top to not cause merge conflicts. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
commit
760a52e80f
|
@ -287,6 +287,8 @@ local_ops.txt
|
|||
- semantics and behavior of local atomic operations.
|
||||
lockdep-design.txt
|
||||
- documentation on the runtime locking correctness validator.
|
||||
locking/
|
||||
- directory with info about kernel locking primitives
|
||||
lockstat.txt
|
||||
- info on collecting statistics on locks (and contention).
|
||||
lockup-watchdogs.txt
|
||||
|
|
|
@ -85,14 +85,6 @@ Description:
|
|||
will be compacted. When it completes, memory will be freed
|
||||
into blocks which have as many contiguous pages as possible
|
||||
|
||||
What: /sys/devices/system/node/nodeX/scan_unevictable_pages
|
||||
Date: October 2008
|
||||
Contact: Lee Schermerhorn <lee.schermerhorn@hp.com>
|
||||
Description:
|
||||
When set, it triggers scanning the node's unevictable lists
|
||||
and move any pages that have become evictable onto the respective
|
||||
zone's inactive list. See mm/vmscan.c
|
||||
|
||||
What: /sys/devices/system/node/nodeX/hugepages/hugepages-<size>/
|
||||
Date: December 2009
|
||||
Contact: Lee Schermerhorn <lee.schermerhorn@hp.com>
|
||||
|
|
|
@ -53,6 +53,14 @@ Description:
|
|||
512 bytes of data.
|
||||
|
||||
|
||||
What: /sys/block/<disk>/integrity/device_is_integrity_capable
|
||||
Date: July 2014
|
||||
Contact: Martin K. Petersen <martin.petersen@oracle.com>
|
||||
Description:
|
||||
Indicates whether a storage device is capable of storing
|
||||
integrity metadata. Set if the device is T10 PI-capable.
|
||||
|
||||
|
||||
What: /sys/block/<disk>/integrity/write_generate
|
||||
Date: June 2008
|
||||
Contact: Martin K. Petersen <martin.petersen@oracle.com>
|
||||
|
|
|
@ -77,11 +77,14 @@ What: /sys/block/zram<id>/notify_free
|
|||
Date: August 2010
|
||||
Contact: Nitin Gupta <ngupta@vflare.org>
|
||||
Description:
|
||||
The notify_free file is read-only and specifies the number of
|
||||
swap slot free notifications received by this device. These
|
||||
notifications are sent to a swap block device when a swap slot
|
||||
is freed. This statistic is applicable only when this disk is
|
||||
being used as a swap disk.
|
||||
The notify_free file is read-only. Depending on device usage
|
||||
scenario it may account a) the number of pages freed because
|
||||
of swap slot free notifications or b) the number of pages freed
|
||||
because of REQ_DISCARD requests sent by bio. The former ones
|
||||
are sent to a swap block device when a swap slot is freed, which
|
||||
implies that this disk is being used as a swap disk. The latter
|
||||
ones are sent by filesystem mounted with discard option,
|
||||
whenever some data blocks are getting discarded.
|
||||
|
||||
What: /sys/block/zram<id>/zero_pages
|
||||
Date: August 2010
|
||||
|
@ -119,3 +122,22 @@ Description:
|
|||
efficiency can be calculated using compr_data_size and this
|
||||
statistic.
|
||||
Unit: bytes
|
||||
|
||||
What: /sys/block/zram<id>/mem_used_max
|
||||
Date: August 2014
|
||||
Contact: Minchan Kim <minchan@kernel.org>
|
||||
Description:
|
||||
The mem_used_max file is read/write and specifies the amount
|
||||
of maximum memory zram have consumed to store compressed data.
|
||||
For resetting the value, you should write "0". Otherwise,
|
||||
you could see -EINVAL.
|
||||
Unit: bytes
|
||||
|
||||
What: /sys/block/zram<id>/mem_limit
|
||||
Date: August 2014
|
||||
Contact: Minchan Kim <minchan@kernel.org>
|
||||
Description:
|
||||
The mem_limit file is read/write and specifies the maximum
|
||||
amount of memory ZRAM can use to store the compressed data. The
|
||||
limit could be changed in run time and "0" means disable the
|
||||
limit. No limit is the initial state. Unit: bytes
|
||||
|
|
|
@ -27,575 +27,62 @@ Description: Generic performance monitoring events
|
|||
"basename".
|
||||
|
||||
|
||||
What: /sys/devices/cpu/events/PM_1PLUS_PPC_CMPL
|
||||
/sys/devices/cpu/events/PM_BRU_FIN
|
||||
/sys/devices/cpu/events/PM_BR_MPRED
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_BRU
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_DCACHE_MISS
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_DFU
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_DIV
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_ERAT_MISS
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_FXU
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_IFU
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_LSU
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_REJECT
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_SCALAR
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_SCALAR_LONG
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_STORE
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_THRD
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_VECTOR
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_VECTOR_LONG
|
||||
/sys/devices/cpu/events/PM_CYC
|
||||
/sys/devices/cpu/events/PM_GCT_NOSLOT_BR_MPRED
|
||||
/sys/devices/cpu/events/PM_GCT_NOSLOT_BR_MPRED_IC_MISS
|
||||
/sys/devices/cpu/events/PM_GCT_NOSLOT_CYC
|
||||
/sys/devices/cpu/events/PM_GCT_NOSLOT_IC_MISS
|
||||
/sys/devices/cpu/events/PM_GRP_CMPL
|
||||
/sys/devices/cpu/events/PM_INST_CMPL
|
||||
/sys/devices/cpu/events/PM_LD_MISS_L1
|
||||
/sys/devices/cpu/events/PM_LD_REF_L1
|
||||
/sys/devices/cpu/events/PM_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_RUN_INST_CMPL
|
||||
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_ALL
|
||||
/sys/devices/cpu/events/PM_GCT_UTIL_7_TO_10_SLOTS
|
||||
/sys/devices/cpu/events/PM_PMC2_SAVED
|
||||
/sys/devices/cpu/events/PM_VSU0_16FLOP
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_DERAT_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_ST_CMPL
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR3_ADD
|
||||
/sys/devices/cpu/events/PM_L2_ST_DISP
|
||||
/sys/devices/cpu/events/PM_L2_CASTOUT_MOD
|
||||
/sys/devices/cpu/events/PM_ISEG
|
||||
/sys/devices/cpu/events/PM_MRK_INST_TIMEO
|
||||
/sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_ADDR
|
||||
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM
|
||||
/sys/devices/cpu/events/PM_IERAT_WR_64K
|
||||
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_16M
|
||||
/sys/devices/cpu/events/PM_IERAT_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_FLOP
|
||||
/sys/devices/cpu/events/PM_THRD_PRIO_4_5_CYC
|
||||
/sys/devices/cpu/events/PM_BR_PRED_TA
|
||||
/sys/devices/cpu/events/PM_EXT_INT
|
||||
/sys/devices/cpu/events/PM_VSU_FSQRT_FDIV
|
||||
/sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC
|
||||
/sys/devices/cpu/events/PM_LSU1_LDF
|
||||
/sys/devices/cpu/events/PM_IC_WRITE_ALL
|
||||
/sys/devices/cpu/events/PM_LSU0_SRQ_STFWD
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_VSU1_SCAL_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_VSU0_8FLOP
|
||||
/sys/devices/cpu/events/PM_POWER_EVENT1
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD_BAL
|
||||
/sys/devices/cpu/events/PM_VSU1_2FLOP
|
||||
/sys/devices/cpu/events/PM_LWSYNC_HELD
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_IERAT_XLATE_WR_16MPLUS
|
||||
/sys/devices/cpu/events/PM_IC_REQ_ALL
|
||||
/sys/devices/cpu/events/PM_DSLB_MISS
|
||||
/sys/devices/cpu/events/PM_L3_MISS
|
||||
/sys/devices/cpu/events/PM_LSU0_L1_PREF
|
||||
/sys/devices/cpu/events/PM_VSU_SCALAR_SINGLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE
|
||||
/sys/devices/cpu/events/PM_L2_INST
|
||||
/sys/devices/cpu/events/PM_VSU0_FRSP
|
||||
/sys/devices/cpu/events/PM_FLUSH_DISP
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_VSU1_DQ_ISSUED
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_LSU_FLUSH_ULD
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_16M
|
||||
/sys/devices/cpu/events/PM_THRD_ALL_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_MEM0_PREFETCH_DISP
|
||||
/sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC_COUNT
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_VSU_FRSP
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_PMC1_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_VSU0_SINGLE
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_VSU0_VECTOR_SP_ISSUED
|
||||
/sys/devices/cpu/events/PM_VSU1_FEST
|
||||
/sys/devices/cpu/events/PM_MRK_INST_DISP
|
||||
/sys/devices/cpu/events/PM_VSU0_COMPLEX_ISSUED
|
||||
/sys/devices/cpu/events/PM_LSU1_FLUSH_UST
|
||||
/sys/devices/cpu/events/PM_FXU_IDLE
|
||||
/sys/devices/cpu/events/PM_LSU0_FLUSH_ULD
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC
|
||||
/sys/devices/cpu/events/PM_LSU1_REJECT_LMQ_FULL
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_INST_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_SHL_CREATED
|
||||
/sys/devices/cpu/events/PM_L2_ST_HIT
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_L3_LD_MISS
|
||||
/sys/devices/cpu/events/PM_FXU1_BUSY_FXU0_IDLE
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD_RES
|
||||
/sys/devices/cpu/events/PM_L2_SN_SX_I_DONE
|
||||
/sys/devices/cpu/events/PM_STCX_CMPL
|
||||
/sys/devices/cpu/events/PM_VSU0_2FLOP
|
||||
/sys/devices/cpu/events/PM_L3_PREF_MISS
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_SYNC_CYC
|
||||
/sys/devices/cpu/events/PM_LSU_REJECT_ERAT_MISS
|
||||
/sys/devices/cpu/events/PM_L1_ICACHE_MISS
|
||||
/sys/devices/cpu/events/PM_LSU1_FLUSH_SRQ
|
||||
/sys/devices/cpu/events/PM_LD_REF_L1_LSU0
|
||||
/sys/devices/cpu/events/PM_VSU0_FEST
|
||||
/sys/devices/cpu/events/PM_VSU_VECTOR_SINGLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_FREQ_UP
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_LSU1_LDX
|
||||
/sys/devices/cpu/events/PM_PMC3_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_MRK_BR_MPRED
|
||||
/sys/devices/cpu/events/PM_SHL_MATCH
|
||||
/sys/devices/cpu/events/PM_MRK_BR_TAKEN
|
||||
/sys/devices/cpu/events/PM_ISLB_MISS
|
||||
/sys/devices/cpu/events/PM_DISP_HELD_THERMAL
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_LSU1_SRQ_STFWD
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_VSU_2FLOP
|
||||
/sys/devices/cpu/events/PM_GCT_FULL_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3_CYC
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_S0_ALLOC
|
||||
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_4K
|
||||
/sys/devices/cpu/events/PM_BR_MPRED_TA
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_DPU_HELD_POWER
|
||||
/sys/devices/cpu/events/PM_MRK_VSU_FIN
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_S0_VALID
|
||||
/sys/devices/cpu/events/PM_GCT_EMPTY_CYC
|
||||
/sys/devices/cpu/events/PM_IOPS_DISP
|
||||
/sys/devices/cpu/events/PM_RUN_SPURR
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_VSU0_1FLOP
|
||||
/sys/devices/cpu/events/PM_SNOOP_TLBIE
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_VSU_SINGLE
|
||||
/sys/devices/cpu/events/PM_DTLB_MISS_16G
|
||||
/sys/devices/cpu/events/PM_FLUSH
|
||||
/sys/devices/cpu/events/PM_L2_LD_HIT
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR2_AND
|
||||
/sys/devices/cpu/events/PM_VSU1_1FLOP
|
||||
/sys/devices/cpu/events/PM_IC_PREF_REQ
|
||||
/sys/devices/cpu/events/PM_L3_LD_HIT
|
||||
/sys/devices/cpu/events/PM_DISP_HELD
|
||||
/sys/devices/cpu/events/PM_L2_LD
|
||||
/sys/devices/cpu/events/PM_LSU_FLUSH_SRQ
|
||||
/sys/devices/cpu/events/PM_BC_PLUS_8_CONV
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD_CYC
|
||||
/sys/devices/cpu/events/PM_L2_RCST_BUSY_RC_FULL
|
||||
/sys/devices/cpu/events/PM_TB_BIT_TRANS
|
||||
/sys/devices/cpu/events/PM_THERMAL_MAX
|
||||
/sys/devices/cpu/events/PM_LSU1_FLUSH_ULD
|
||||
/sys/devices/cpu/events/PM_LSU1_REJECT_LHS
|
||||
/sys/devices/cpu/events/PM_LSU_LRQ_S0_ALLOC
|
||||
/sys/devices/cpu/events/PM_L3_CO_L31
|
||||
/sys/devices/cpu/events/PM_POWER_EVENT4
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_BR_UNCOND
|
||||
/sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_ALLOC
|
||||
/sys/devices/cpu/events/PM_PMC4_REWIND
|
||||
/sys/devices/cpu/events/PM_L2_RCLD_DISP
|
||||
/sys/devices/cpu/events/PM_THRD_PRIO_2_3_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BHT_REDIRECT
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_L2
|
||||
/sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC_COUNT
|
||||
/sys/devices/cpu/events/PM_BR_PRED_CCACHE
|
||||
/sys/devices/cpu/events/PM_GCT_UTIL_1_TO_2_SLOTS
|
||||
/sys/devices/cpu/events/PM_MRK_ST_CMPL_INT
|
||||
/sys/devices/cpu/events/PM_LSU_TWO_TABLEWALK_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_LSU_SET_MPRED
|
||||
/sys/devices/cpu/events/PM_FLUSH_DISP_TLBIE
|
||||
/sys/devices/cpu/events/PM_VSU1_FCONV
|
||||
/sys/devices/cpu/events/PM_DERAT_MISS_16G
|
||||
/sys/devices/cpu/events/PM_INST_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_REDIRECT
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L2
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L2
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_4K
|
||||
/sys/devices/cpu/events/PM_VSU0_FPSCR
|
||||
/sys/devices/cpu/events/PM_VSU1_VECT_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_MEM0_RQ_DISP
|
||||
/sys/devices/cpu/events/PM_L2_LD_MISS
|
||||
/sys/devices/cpu/events/PM_VMX_RESULT_SAT_1
|
||||
/sys/devices/cpu/events/PM_L1_PREF
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM_CYC
|
||||
/sys/devices/cpu/events/PM_GRP_IC_MISS_NONSPEC
|
||||
/sys/devices/cpu/events/PM_PB_NODE_PUMP
|
||||
/sys/devices/cpu/events/PM_SHL_MERGED
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR1_ADD
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L3
|
||||
/sys/devices/cpu/events/PM_LSU_FLUSH
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_SYNC_COUNT
|
||||
/sys/devices/cpu/events/PM_PMC2_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_LSU_LDF
|
||||
/sys/devices/cpu/events/PM_POWER_EVENT3
|
||||
/sys/devices/cpu/events/PM_DISP_WT
|
||||
/sys/devices/cpu/events/PM_IC_BANK_CONFLICT
|
||||
/sys/devices/cpu/events/PM_BR_MPRED_CR_TA
|
||||
/sys/devices/cpu/events/PM_L2_INST_MISS
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR2_ADD
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH
|
||||
/sys/devices/cpu/events/PM_L2_LDST
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_VSU0_FIN
|
||||
/sys/devices/cpu/events/PM_VSU1_FCONV
|
||||
/sys/devices/cpu/events/PM_INST_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD_TLBIE
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM_CYC
|
||||
/sys/devices/cpu/events/PM_BR_PRED_CR
|
||||
/sys/devices/cpu/events/PM_LSU_REJECT
|
||||
/sys/devices/cpu/events/PM_GCT_UTIL_3_TO_6_SLOTS
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_END_GCT_NOSLOT
|
||||
/sys/devices/cpu/events/PM_LSU0_REJECT_LMQ_FULL
|
||||
/sys/devices/cpu/events/PM_VSU_FEST
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR0_AND
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L3
|
||||
/sys/devices/cpu/events/PM_POWER_EVENT2
|
||||
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_PAGE
|
||||
/sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV
|
||||
/sys/devices/cpu/events/PM_MRK_GRP_CMPL
|
||||
/sys/devices/cpu/events/PM_VSU0_SCAL_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_GRP_DISP
|
||||
/sys/devices/cpu/events/PM_LSU0_LDX
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L2
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_VSU0_VECT_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_VSU1_2FLOP_DOUBLE
|
||||
/sys/devices/cpu/events/PM_THRD_PRIO_6_7_CYC
|
||||
/sys/devices/cpu/events/PM_BC_PLUS_8_RSLV_TAKEN
|
||||
/sys/devices/cpu/events/PM_BR_MPRED_CR
|
||||
/sys/devices/cpu/events/PM_L3_CO_MEM
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_FULL_CYC
|
||||
/sys/devices/cpu/events/PM_TABLEWALK_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_STFWD
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_FXU0_FIN
|
||||
/sys/devices/cpu/events/PM_LSU1_L1_SW_PREF
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_PMC5_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_LD_REF_L1_LSU1
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_VSU0_SCAL_SINGLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_BR_MPRED_LSTACK
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD_CYC
|
||||
/sys/devices/cpu/events/PM_LSU0_FLUSH_UST
|
||||
/sys/devices/cpu/events/PM_LSU_NCST
|
||||
/sys/devices/cpu/events/PM_BR_TAKEN
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_DTLB_MISS_4K
|
||||
/sys/devices/cpu/events/PM_PMC4_SAVED
|
||||
/sys/devices/cpu/events/PM_VSU1_PERMUTE_ISSUED
|
||||
/sys/devices/cpu/events/PM_SLB_MISS
|
||||
/sys/devices/cpu/events/PM_LSU1_FLUSH_LRQ
|
||||
/sys/devices/cpu/events/PM_DTLB_MISS
|
||||
/sys/devices/cpu/events/PM_VSU1_FRSP
|
||||
/sys/devices/cpu/events/PM_VSU_VECTOR_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_L2_CASTOUT_SHR
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_VSU1_STF
|
||||
/sys/devices/cpu/events/PM_ST_FIN
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_L2_LOC_GUESS_WRONG
|
||||
/sys/devices/cpu/events/PM_MRK_STCX_FAIL
|
||||
/sys/devices/cpu/events/PM_LSU0_REJECT_LHS
|
||||
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_HIT
|
||||
/sys/devices/cpu/events/PM_L3_PREF_BUSY
|
||||
/sys/devices/cpu/events/PM_MRK_BRU_FIN
|
||||
/sys/devices/cpu/events/PM_LSU1_NCLD
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_LSU_NCLD
|
||||
/sys/devices/cpu/events/PM_LSU_LDX
|
||||
/sys/devices/cpu/events/PM_L2_LOC_GUESS_CORRECT
|
||||
/sys/devices/cpu/events/PM_THRESH_TIMEO
|
||||
/sys/devices/cpu/events/PM_L3_PREF_ST
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD_SYNC
|
||||
/sys/devices/cpu/events/PM_VSU_SIMPLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_VSU1_SINGLE
|
||||
/sys/devices/cpu/events/PM_DATA_TABLEWALK_CYC
|
||||
/sys/devices/cpu/events/PM_L2_RC_ST_DONE
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_MOD
|
||||
/sys/devices/cpu/events/PM_LARX_LSU1
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD
|
||||
/sys/devices/cpu/events/PM_DERAT_MISS_4K
|
||||
/sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_ADDR
|
||||
/sys/devices/cpu/events/PM_SEG_EXCEPTION
|
||||
/sys/devices/cpu/events/PM_FLUSH_DISP_SB
|
||||
/sys/devices/cpu/events/PM_L2_DC_INV
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_DSEG
|
||||
/sys/devices/cpu/events/PM_BR_PRED_LSTACK
|
||||
/sys/devices/cpu/events/PM_VSU0_STF
|
||||
/sys/devices/cpu/events/PM_LSU_FX_FIN
|
||||
/sys/devices/cpu/events/PM_DERAT_MISS_16M
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_GCT_UTIL_11_PLUS_SLOTS
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L3
|
||||
/sys/devices/cpu/events/PM_MRK_IFU_FIN
|
||||
/sys/devices/cpu/events/PM_ITLB_MISS
|
||||
/sys/devices/cpu/events/PM_VSU_STF
|
||||
/sys/devices/cpu/events/PM_LSU_FLUSH_UST
|
||||
/sys/devices/cpu/events/PM_L2_LDST_MISS
|
||||
/sys/devices/cpu/events/PM_FXU1_FIN
|
||||
/sys/devices/cpu/events/PM_SHL_DEALLOCATED
|
||||
/sys/devices/cpu/events/PM_L2_SN_M_WR_DONE
|
||||
/sys/devices/cpu/events/PM_LSU_REJECT_SET_MPRED
|
||||
/sys/devices/cpu/events/PM_L3_PREF_LD
|
||||
/sys/devices/cpu/events/PM_L2_SN_M_RD_DONE
|
||||
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_16G
|
||||
/sys/devices/cpu/events/PM_VSU_FCONV
|
||||
/sys/devices/cpu/events/PM_ANY_THRD_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_LSU_LMQ_FULL_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_REJECT_LHS
|
||||
/sys/devices/cpu/events/PM_MRK_LD_MISS_L1_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2_CYC
|
||||
/sys/devices/cpu/events/PM_INST_IMC_MATCH_DISP
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM_CYC
|
||||
/sys/devices/cpu/events/PM_VSU0_SIMPLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_VSU_FMA_DOUBLE
|
||||
/sys/devices/cpu/events/PM_VSU_4FLOP
|
||||
/sys/devices/cpu/events/PM_VSU1_FIN
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR1_AND
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_RMEM
|
||||
/sys/devices/cpu/events/PM_LSU_LRQ_S0_VALID
|
||||
/sys/devices/cpu/events/PM_LSU0_LDF
|
||||
/sys/devices/cpu/events/PM_FLUSH_COMPLETION
|
||||
/sys/devices/cpu/events/PM_ST_MISS_L1
|
||||
/sys/devices/cpu/events/PM_L2_NODE_PUMP
|
||||
/sys/devices/cpu/events/PM_INST_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC
|
||||
/sys/devices/cpu/events/PM_VSU1_DENORM
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR_CYC
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR0_ADD
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_EE_OFF_EXT_INT
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_INST_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_PMC6_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_VSU_2FLOP_DOUBLE
|
||||
/sys/devices/cpu/events/PM_TLB_MISS
|
||||
/sys/devices/cpu/events/PM_FXU_BUSY
|
||||
/sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_OTHER
|
||||
/sys/devices/cpu/events/PM_LSU_REJECT_LMQ_FULL
|
||||
/sys/devices/cpu/events/PM_IC_RELOAD_SHR
|
||||
/sys/devices/cpu/events/PM_GRP_MRK
|
||||
/sys/devices/cpu/events/PM_MRK_ST_NEST
|
||||
/sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV
|
||||
/sys/devices/cpu/events/PM_LSU0_FLUSH_LRQ
|
||||
/sys/devices/cpu/events/PM_LARX_LSU0
|
||||
/sys/devices/cpu/events/PM_IBUF_FULL_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR_CYC
|
||||
/sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_ALLOC
|
||||
/sys/devices/cpu/events/PM_GRP_MRK_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR_CYC
|
||||
/sys/devices/cpu/events/PM_L2_GLOB_GUESS_CORRECT
|
||||
/sys/devices/cpu/events/PM_LSU_REJECT_LHS
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L3
|
||||
/sys/devices/cpu/events/PM_FREQ_DOWN
|
||||
/sys/devices/cpu/events/PM_PB_RETRY_NODE_PUMP
|
||||
/sys/devices/cpu/events/PM_INST_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_MRK_INST_ISSUED
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_RUN_PURR
|
||||
/sys/devices/cpu/events/PM_MRK_GRP_IC_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L3
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_LSU_FLUSH_LRQ
|
||||
/sys/devices/cpu/events/PM_MRK_DERAT_MISS_64K
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_MOD
|
||||
/sys/devices/cpu/events/PM_L2_ST_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_LWSYNC
|
||||
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_LRQ
|
||||
/sys/devices/cpu/events/PM_INST_IMC_MATCH_CMPL
|
||||
/sys/devices/cpu/events/PM_NEST_PAIR3_AND
|
||||
/sys/devices/cpu/events/PM_PB_RETRY_SYS_PUMP
|
||||
/sys/devices/cpu/events/PM_MRK_INST_FIN
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_64K
|
||||
/sys/devices/cpu/events/PM_LSU_FIN
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_REJECT
|
||||
/sys/devices/cpu/events/PM_L2_CO_FAIL_BUSY
|
||||
/sys/devices/cpu/events/PM_MEM0_WQ_DISP
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_THERMAL_WARN
|
||||
/sys/devices/cpu/events/PM_VSU0_4FLOP
|
||||
/sys/devices/cpu/events/PM_BR_MPRED_CCACHE
|
||||
/sys/devices/cpu/events/PM_L1_DEMAND_WRITE
|
||||
/sys/devices/cpu/events/PM_FLUSH_BR_MPRED
|
||||
/sys/devices/cpu/events/PM_MRK_DTLB_MISS_16G
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_L2_RCST_DISP
|
||||
/sys/devices/cpu/events/PM_LSU_PARTIAL_CDF
|
||||
/sys/devices/cpu/events/PM_DISP_CLB_HELD_SB
|
||||
/sys/devices/cpu/events/PM_VSU0_FMA_DOUBLE
|
||||
/sys/devices/cpu/events/PM_FXU0_BUSY_FXU1_IDLE
|
||||
/sys/devices/cpu/events/PM_IC_DEMAND_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_UST
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L3MISS
|
||||
/sys/devices/cpu/events/PM_VSU_DENORM
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_PARTIAL_CDF
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_IC_PREF_WRITE
|
||||
/sys/devices/cpu/events/PM_BR_PRED
|
||||
/sys/devices/cpu/events/PM_INST_FROM_DMEM
|
||||
/sys/devices/cpu/events/PM_IC_PREF_CANCEL_ALL
|
||||
/sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_CONFIRM
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_SRQ
|
||||
/sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC
|
||||
/sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_OTHER
|
||||
/sys/devices/cpu/events/PM_VSU1_DD_ISSUED
|
||||
/sys/devices/cpu/events/PM_PTEG_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L21_SHR
|
||||
/sys/devices/cpu/events/PM_LSU0_NCLD
|
||||
/sys/devices/cpu/events/PM_VSU1_4FLOP
|
||||
/sys/devices/cpu/events/PM_VSU1_8FLOP
|
||||
/sys/devices/cpu/events/PM_VSU_8FLOP
|
||||
/sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_CYC
|
||||
/sys/devices/cpu/events/PM_DTLB_MISS_64K
|
||||
/sys/devices/cpu/events/PM_THRD_CONC_RUN_INST
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2
|
||||
/sys/devices/cpu/events/PM_PB_SYS_PUMP
|
||||
/sys/devices/cpu/events/PM_VSU_FIN
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_THRD_PRIO_0_1_CYC
|
||||
/sys/devices/cpu/events/PM_DERAT_MISS_64K
|
||||
/sys/devices/cpu/events/PM_PMC2_REWIND
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L2
|
||||
/sys/devices/cpu/events/PM_GRP_BR_MPRED_NONSPEC
|
||||
/sys/devices/cpu/events/PM_INST_DISP
|
||||
/sys/devices/cpu/events/PM_MEM0_RD_CANCEL_TOTAL
|
||||
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM
|
||||
/sys/devices/cpu/events/PM_L1_DCACHE_RELOAD_VALID
|
||||
/sys/devices/cpu/events/PM_VSU_SCALAR_DOUBLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_L3_PREF_HIT
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_MOD
|
||||
/sys/devices/cpu/events/PM_MRK_FXU_FIN
|
||||
/sys/devices/cpu/events/PM_PMC4_OVERFLOW
|
||||
/sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3
|
||||
/sys/devices/cpu/events/PM_LSU0_LMQ_LHR_MERGE
|
||||
/sys/devices/cpu/events/PM_BTAC_HIT
|
||||
/sys/devices/cpu/events/PM_L3_RD_BUSY
|
||||
/sys/devices/cpu/events/PM_LSU0_L1_SW_PREF
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_ALLOC
|
||||
/sys/devices/cpu/events/PM_L2_ST
|
||||
/sys/devices/cpu/events/PM_VSU0_DENORM
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_BR_PRED_CR_TA
|
||||
/sys/devices/cpu/events/PM_VSU0_FCONV
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FLUSH_ULD
|
||||
/sys/devices/cpu/events/PM_BTAC_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC_COUNT
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2
|
||||
/sys/devices/cpu/events/PM_LSU_DCACHE_RELOAD_VALID
|
||||
/sys/devices/cpu/events/PM_VSU_FMA
|
||||
/sys/devices/cpu/events/PM_LSU0_FLUSH_SRQ
|
||||
/sys/devices/cpu/events/PM_LSU1_L1_PREF
|
||||
/sys/devices/cpu/events/PM_IOPS_CMPL
|
||||
/sys/devices/cpu/events/PM_L2_SYS_PUMP
|
||||
/sys/devices/cpu/events/PM_L2_RCLD_BUSY_RC_FULL
|
||||
/sys/devices/cpu/events/PM_LSU_LMQ_S0_ALLOC
|
||||
/sys/devices/cpu/events/PM_FLUSH_DISP_SYNC
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD_CYC
|
||||
/sys/devices/cpu/events/PM_L2_IC_INV
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD_CYC
|
||||
/sys/devices/cpu/events/PM_L3_PREF_LDST
|
||||
/sys/devices/cpu/events/PM_LSU_SRQ_EMPTY_CYC
|
||||
/sys/devices/cpu/events/PM_LSU_LMQ_S0_VALID
|
||||
/sys/devices/cpu/events/PM_FLUSH_PARTIAL
|
||||
/sys/devices/cpu/events/PM_VSU1_FMA_DOUBLE
|
||||
/sys/devices/cpu/events/PM_1PLUS_PPC_DISP
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_SUSPENDED
|
||||
/sys/devices/cpu/events/PM_VSU0_FMA
|
||||
/sys/devices/cpu/events/PM_STCX_FAIL
|
||||
/sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV_DOUBLE
|
||||
/sys/devices/cpu/events/PM_DC_PREF_DST
|
||||
/sys/devices/cpu/events/PM_VSU1_SCAL_SINGLE_ISSUED
|
||||
/sys/devices/cpu/events/PM_L3_HIT
|
||||
/sys/devices/cpu/events/PM_L2_GLOB_GUESS_WRONG
|
||||
/sys/devices/cpu/events/PM_MRK_DFU_FIN
|
||||
/sys/devices/cpu/events/PM_INST_FROM_L1
|
||||
/sys/devices/cpu/events/PM_IC_DEMAND_REQ
|
||||
/sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV_DOUBLE
|
||||
/sys/devices/cpu/events/PM_VSU1_FMA
|
||||
/sys/devices/cpu/events/PM_MRK_LD_MISS_L1
|
||||
/sys/devices/cpu/events/PM_VSU0_2FLOP_DOUBLE
|
||||
/sys/devices/cpu/events/PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_SHR
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_REJECT_ERAT_MISS
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_L2MISS
|
||||
/sys/devices/cpu/events/PM_DATA_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_INST_FROM_PREF
|
||||
/sys/devices/cpu/events/PM_VSU1_SQ
|
||||
/sys/devices/cpu/events/PM_L2_LD_DISP
|
||||
/sys/devices/cpu/events/PM_L2_DISP_ALL
|
||||
/sys/devices/cpu/events/PM_THRD_GRP_CMPL_BOTH_CYC
|
||||
/sys/devices/cpu/events/PM_VSU_FSQRT_FDIV_DOUBLE
|
||||
/sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_VSU_1FLOP
|
||||
/sys/devices/cpu/events/PM_HV_CYC
|
||||
/sys/devices/cpu/events/PM_MRK_LSU_FIN
|
||||
/sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR
|
||||
/sys/devices/cpu/events/PM_DTLB_MISS_16M
|
||||
/sys/devices/cpu/events/PM_LSU1_LMQ_LHR_MERGE
|
||||
/sys/devices/cpu/events/PM_IFU_FIN
|
||||
/sys/devices/cpu/events/PM_1THRD_CON_RUN_INSTR
|
||||
/sys/devices/cpu/events/PM_CMPLU_STALL_COUNT
|
||||
/sys/devices/cpu/events/PM_MEM0_PB_RD_CL
|
||||
/sys/devices/cpu/events/PM_THRD_1_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_THRD_2_CONC_RUN_INSTR
|
||||
/sys/devices/cpu/events/PM_THRD_2_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_THRD_3_CONC_RUN_INST
|
||||
/sys/devices/cpu/events/PM_THRD_3_RUN_CYC
|
||||
/sys/devices/cpu/events/PM_THRD_4_CONC_RUN_INST
|
||||
/sys/devices/cpu/events/PM_THRD_4_RUN_CYC
|
||||
|
||||
Date: 2013/01/08
|
||||
|
||||
What: /sys/bus/event_source/devices/<pmu>/events/<event>
|
||||
Date: 2014/02/24
|
||||
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
|
||||
Linux Powerpc mailing list <linuxppc-dev@ozlabs.org>
|
||||
Description: Per-pmu performance monitoring events specific to the running system
|
||||
|
||||
Description: POWER-systems specific performance monitoring events
|
||||
Each file (except for some of those with a '.' in them, '.unit'
|
||||
and '.scale') in the 'events' directory describes a single
|
||||
performance monitoring event supported by the <pmu>. The name
|
||||
of the file is the name of the event.
|
||||
|
||||
A collection of performance monitoring events that may be
|
||||
supported by the POWER CPU. These events can be monitored
|
||||
using the 'perf(1)' tool.
|
||||
File contents:
|
||||
|
||||
These events may not be supported by other CPUs.
|
||||
<term>[=<value>][,<term>[=<value>]]...
|
||||
|
||||
The contents of each file would look like:
|
||||
Where <term> is one of the terms listed under
|
||||
/sys/bus/event_source/devices/<pmu>/format/ and <value> is
|
||||
a number is base-16 format with a '0x' prefix (lowercase only).
|
||||
If a <term> is specified alone (without an assigned value), it
|
||||
is implied that 0x1 is assigned to that <term>.
|
||||
|
||||
event=0xNNNN
|
||||
Examples (each of these lines would be in a seperate file):
|
||||
|
||||
where 'N' is a hex digit and the number '0xNNNN' shows the
|
||||
"raw code" for the perf event identified by the file's
|
||||
"basename".
|
||||
event=0x2abc
|
||||
event=0x423,inv,cmask=0x3
|
||||
domain=0x1,offset=0x8,starting_index=0xffff
|
||||
|
||||
Further, multiple terms like 'event=0xNNNN' can be specified
|
||||
and separated with comma. All available terms are defined in
|
||||
the /sys/bus/event_source/devices/<dev>/format file.
|
||||
Each of the assignments indicates a value to be assigned to a
|
||||
particular set of bits (as defined by the format file
|
||||
corresponding to the <term>) in the perf_event structure passed
|
||||
to the perf_open syscall.
|
||||
|
||||
What: /sys/bus/event_source/devices/<pmu>/events/<event>.unit
|
||||
Date: 2014/02/24
|
||||
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
|
||||
Description: Perf event units
|
||||
|
||||
A string specifying the English plural numerical unit that <event>
|
||||
(once multiplied by <event>.scale) represents.
|
||||
|
||||
Example:
|
||||
|
||||
Joules
|
||||
|
||||
What: /sys/bus/event_source/devices/<pmu>/events/<event>.scale
|
||||
Date: 2014/02/24
|
||||
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
|
||||
Description: Perf event scaling factors
|
||||
|
||||
A string representing a floating point value expressed in
|
||||
scientific notation to be multiplied by the event count
|
||||
recieved from the kernel to match the unit specified in the
|
||||
<event>.unit file.
|
||||
|
||||
Example:
|
||||
|
||||
2.3283064365386962890625e-10
|
||||
|
||||
This is provided to avoid performing floating point arithmetic
|
||||
in the kernel.
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
Provides access to the binary "24x7 catalog" provided by the
|
||||
hypervisor on POWER7 and 8 systems. This catalog lists events
|
||||
|
@ -10,14 +10,14 @@ Description:
|
|||
|
||||
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog_length
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
A number equal to the length in bytes of the catalog. This is
|
||||
also extractable from the provided binary "catalog" sysfs entry.
|
||||
|
||||
What: /sys/bus/event_source/devices/hv_24x7/interface/catalog_version
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
Exposes the "version" field of the 24x7 catalog. This is also
|
||||
extractable from the provided binary "catalog" sysfs entry.
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
What: /sys/bus/event_source/devices/hv_gpci/interface/collect_privileged
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
'0' if the hypervisor is configured to forbid access to event
|
||||
counters being accumulated by other guests and to physical
|
||||
|
@ -9,35 +9,35 @@ Description:
|
|||
|
||||
What: /sys/bus/event_source/devices/hv_gpci/interface/ga
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
0 or 1. Indicates whether we have access to "GA" events (listed
|
||||
in arch/powerpc/perf/hv-gpci.h).
|
||||
|
||||
What: /sys/bus/event_source/devices/hv_gpci/interface/expanded
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
0 or 1. Indicates whether we have access to "EXPANDED" events (listed
|
||||
in arch/powerpc/perf/hv-gpci.h).
|
||||
|
||||
What: /sys/bus/event_source/devices/hv_gpci/interface/lab
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
0 or 1. Indicates whether we have access to "LAB" events (listed
|
||||
in arch/powerpc/perf/hv-gpci.h).
|
||||
|
||||
What: /sys/bus/event_source/devices/hv_gpci/interface/version
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
A number indicating the version of the gpci interface that the
|
||||
hypervisor reports supporting.
|
||||
|
||||
What: /sys/bus/event_source/devices/hv_gpci/interface/kernel_version
|
||||
Date: February 2014
|
||||
Contact: Cody P Schafer <cody@linux.vnet.ibm.com>
|
||||
Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
|
||||
Description:
|
||||
A number indicating the latest version of the gpci interface
|
||||
that the kernel is aware of.
|
||||
|
|
|
@ -65,6 +65,16 @@ Description:
|
|||
force a rescan of all PCI buses in the system, and
|
||||
re-discover previously removed devices.
|
||||
|
||||
What: /sys/bus/pci/devices/.../msi_bus
|
||||
Date: September 2014
|
||||
Contact: Linux PCI developers <linux-pci@vger.kernel.org>
|
||||
Description:
|
||||
Writing a zero value to this attribute disallows MSI and
|
||||
MSI-X for any future drivers of the device. If the device
|
||||
is a bridge, MSI and MSI-X will be disallowed for future
|
||||
drivers of all child devices under the bridge. Drivers
|
||||
must be reloaded for the new setting to take effect.
|
||||
|
||||
What: /sys/bus/pci/devices/.../msi_irqs/
|
||||
Date: September, 2011
|
||||
Contact: Neil Horman <nhorman@tuxdriver.com>
|
||||
|
|
129
Documentation/ABI/testing/sysfs-class-cxl
Normal file
129
Documentation/ABI/testing/sysfs-class-cxl
Normal file
|
@ -0,0 +1,129 @@
|
|||
Slave contexts (eg. /sys/class/cxl/afu0.0s):
|
||||
|
||||
What: /sys/class/cxl/<afu>/irqs_max
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read/write
|
||||
Decimal value of maximum number of interrupts that can be
|
||||
requested by userspace. The default on probe is the maximum
|
||||
that hardware can support (eg. 2037). Write values will limit
|
||||
userspace applications to that many userspace interrupts. Must
|
||||
be >= irqs_min.
|
||||
|
||||
What: /sys/class/cxl/<afu>/irqs_min
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the minimum number of interrupts that
|
||||
userspace must request on a CXL_START_WORK ioctl. Userspace may
|
||||
omit the num_interrupts field in the START_WORK IOCTL to get
|
||||
this minimum automatically.
|
||||
|
||||
What: /sys/class/cxl/<afu>/mmio_size
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the size of the MMIO space that may be mmaped
|
||||
by userspace.
|
||||
|
||||
What: /sys/class/cxl/<afu>/modes_supported
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
List of the modes this AFU supports. One per line.
|
||||
Valid entries are: "dedicated_process" and "afu_directed"
|
||||
|
||||
What: /sys/class/cxl/<afu>/mode
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read/write
|
||||
The current mode the AFU is using. Will be one of the modes
|
||||
given in modes_supported. Writing will change the mode
|
||||
provided that no user contexts are attached.
|
||||
|
||||
|
||||
What: /sys/class/cxl/<afu>/prefault_mode
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read/write
|
||||
Set the mode for prefaulting in segments into the segment table
|
||||
when performing the START_WORK ioctl. Possible values:
|
||||
none: No prefaulting (default)
|
||||
work_element_descriptor: Treat the work element
|
||||
descriptor as an effective address and
|
||||
prefault what it points to.
|
||||
all: all segments process calling START_WORK maps.
|
||||
|
||||
What: /sys/class/cxl/<afu>/reset
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: write only
|
||||
Writing 1 here will reset the AFU provided there are not
|
||||
contexts active on the AFU.
|
||||
|
||||
What: /sys/class/cxl/<afu>/api_version
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the current version of the kernel/user API.
|
||||
|
||||
What: /sys/class/cxl/<afu>/api_version_com
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the the lowest version of the userspace API
|
||||
this this kernel supports.
|
||||
|
||||
|
||||
|
||||
Master contexts (eg. /sys/class/cxl/afu0.0m)
|
||||
|
||||
What: /sys/class/cxl/<afu>m/mmio_size
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the size of the MMIO space that may be mmaped
|
||||
by userspace. This includes all slave contexts space also.
|
||||
|
||||
What: /sys/class/cxl/<afu>m/pp_mmio_len
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the Per Process MMIO space length.
|
||||
|
||||
What: /sys/class/cxl/<afu>m/pp_mmio_off
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the Per Process MMIO space offset.
|
||||
|
||||
|
||||
Card info (eg. /sys/class/cxl/card0)
|
||||
|
||||
What: /sys/class/cxl/<card>/caia_version
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Identifies the CAIA Version the card implements.
|
||||
|
||||
What: /sys/class/cxl/<card>/psl_version
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Identifies the revision level of the PSL.
|
||||
|
||||
What: /sys/class/cxl/<card>/base_image
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Identifies the revision level of the base image for devices
|
||||
that support loadable PSLs. For FPGAs this field identifies
|
||||
the image contained in the on-adapter flash which is loaded
|
||||
during the initial program load.
|
||||
|
||||
What: /sys/class/cxl/<card>/image_loaded
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Will return "user" or "factory" depending on the image loaded
|
||||
onto the card.
|
|
@ -18,3 +18,17 @@ Description:
|
|||
This file is writeable and can be used to set the assumed
|
||||
battery 'full level'. As batteries age, this value has to be
|
||||
amended over time.
|
||||
|
||||
What: /sys/class/power_supply/max14577-charger/device/fast_charge_timer
|
||||
Date: October 2014
|
||||
KernelVersion: 3.18.0
|
||||
Contact: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
Description:
|
||||
This entry shows and sets the maximum time the max14577
|
||||
charger operates in fast-charge mode. When the timer expires
|
||||
the device will terminate fast-charge mode (charging current
|
||||
will drop to 0 A) and will trigger interrupt.
|
||||
|
||||
Valid values:
|
||||
- 5, 6 or 7 (hours),
|
||||
- 0: disabled.
|
||||
|
|
|
@ -61,6 +61,14 @@ Users: hotplug memory remove tools
|
|||
http://www.ibm.com/developerworks/wikis/display/LinuxP/powerpc-utils
|
||||
|
||||
|
||||
What: /sys/devices/system/memory/memoryX/valid_zones
|
||||
Date: July 2014
|
||||
Contact: Zhang Zhen <zhenzhang.zhang@huawei.com>
|
||||
Description:
|
||||
The file /sys/devices/system/memory/memoryX/valid_zones is
|
||||
read-only and is designed to show which zone this memory
|
||||
block can be onlined to.
|
||||
|
||||
What: /sys/devices/system/memoryX/nodeY
|
||||
Date: October 2009
|
||||
Contact: Linux Memory Management list <linux-mm@kvack.org>
|
||||
|
|
|
@ -291,10 +291,9 @@ char *date;</synopsis>
|
|||
<title>Device Registration</title>
|
||||
<para>
|
||||
A number of functions are provided to help with device registration.
|
||||
The functions deal with PCI, USB and platform devices, respectively.
|
||||
The functions deal with PCI and platform devices, respectively.
|
||||
</para>
|
||||
!Edrivers/gpu/drm/drm_pci.c
|
||||
!Edrivers/gpu/drm/drm_usb.c
|
||||
!Edrivers/gpu/drm/drm_platform.c
|
||||
<para>
|
||||
New drivers that no longer rely on the services provided by the
|
||||
|
@ -3386,6 +3385,13 @@ void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis>
|
|||
by scheduling a timer. The delay is accessible through the vblankoffdelay
|
||||
module parameter or the <varname>drm_vblank_offdelay</varname> global
|
||||
variable and expressed in milliseconds. Its default value is 5000 ms.
|
||||
Zero means never disable, and a negative value means disable immediately.
|
||||
Drivers may override the behaviour by setting the
|
||||
<structname>drm_device</structname>
|
||||
<structfield>vblank_disable_immediate</structfield> flag, which when set
|
||||
causes vblank interrupts to be disabled immediately regardless of the
|
||||
drm_vblank_offdelay value. The flag should only be set if there's a
|
||||
properly working hardware vblank counter present.
|
||||
</para>
|
||||
<para>
|
||||
When a vertical blanking interrupt occurs drivers only need to call the
|
||||
|
@ -3400,6 +3406,7 @@ void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis>
|
|||
<sect2>
|
||||
<title>Vertical Blanking and Interrupt Handling Functions Reference</title>
|
||||
!Edrivers/gpu/drm/drm_irq.c
|
||||
!Finclude/drm/drmP.h drm_crtc_vblank_waitqueue
|
||||
</sect2>
|
||||
</sect1>
|
||||
|
||||
|
@ -3918,6 +3925,11 @@ int num_ioctls;</synopsis>
|
|||
!Pdrivers/gpu/drm/i915/i915_cmd_parser.c batch buffer command parser
|
||||
!Idrivers/gpu/drm/i915/i915_cmd_parser.c
|
||||
</sect2>
|
||||
<sect2>
|
||||
<title>Logical Rings, Logical Ring Contexts and Execlists</title>
|
||||
!Pdrivers/gpu/drm/i915/intel_lrc.c Logical Rings, Logical Ring Contexts and Execlists
|
||||
!Idrivers/gpu/drm/i915/intel_lrc.c
|
||||
</sect2>
|
||||
</sect1>
|
||||
</chapter>
|
||||
</part>
|
||||
|
|
|
@ -1972,7 +1972,7 @@ machines due to caching.
|
|||
<itemizedlist>
|
||||
<listitem>
|
||||
<para>
|
||||
<filename>Documentation/spinlocks.txt</filename>:
|
||||
<filename>Documentation/locking/spinlocks.txt</filename>:
|
||||
Linus Torvalds' spinlocking tutorial in the kernel sources.
|
||||
</para>
|
||||
</listitem>
|
||||
|
|
|
@ -2566,6 +2566,12 @@ fields changed from _s32 to _u32.
|
|||
<para>Added compound control types and &VIDIOC-QUERY-EXT-CTRL;.
|
||||
</para>
|
||||
</listitem>
|
||||
<title>V4L2 in Linux 3.18</title>
|
||||
<orderedlist>
|
||||
<listitem>
|
||||
<para>Added <constant>V4L2_CID_PAN_SPEED</constant> and
|
||||
<constant>V4L2_CID_TILT_SPEED</constant> camera controls.</para>
|
||||
</listitem>
|
||||
</orderedlist>
|
||||
</section>
|
||||
|
||||
|
|
|
@ -3965,6 +3965,27 @@ by exposure, white balance or focus controls.</entry>
|
|||
</row>
|
||||
<row><entry></entry></row>
|
||||
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_PAN_SPEED</constant> </entry>
|
||||
<entry>integer</entry>
|
||||
</row><row><entry spanname="descr">This control turns the
|
||||
camera horizontally at the specific speed. The unit is undefined. A
|
||||
positive value moves the camera to the right (clockwise when viewed
|
||||
from above), a negative value to the left. A value of zero stops the motion
|
||||
if one is in progress and has no effect otherwise.</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_TILT_SPEED</constant> </entry>
|
||||
<entry>integer</entry>
|
||||
</row><row><entry spanname="descr">This control turns the
|
||||
camera vertically at the specified speed. The unit is undefined. A
|
||||
positive value moves the camera up, a negative value down. A value of zero
|
||||
stops the motion if one is in progress and has no effect otherwise.</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
|
@ -4790,6 +4811,40 @@ interface and may change in the future.</para>
|
|||
conversion.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_TEST_PATTERN_RED</constant></entry>
|
||||
<entry>integer</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="descr">Test pattern red colour component.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_TEST_PATTERN_GREENR</constant></entry>
|
||||
<entry>integer</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="descr">Test pattern green (next to red)
|
||||
colour component.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_TEST_PATTERN_BLUE</constant></entry>
|
||||
<entry>integer</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="descr">Test pattern blue colour component.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_TEST_PATTERN_GREENB</constant></entry>
|
||||
<entry>integer</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="descr">Test pattern green (next to blue)
|
||||
colour component.
|
||||
</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
|
|
|
@ -237,9 +237,9 @@ for a pixel lie next to each other in memory.</para>
|
|||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-RGB555X">
|
||||
<entry><constant>V4L2_PIX_FMT_RGB555X</constant></entry>
|
||||
<entry>'RGBQ'</entry>
|
||||
<row id="V4L2-PIX-FMT-ARGB555X">
|
||||
<entry><constant>V4L2_PIX_FMT_ARGB555X</constant></entry>
|
||||
<entry>'AR15' | (1 << 31)</entry>
|
||||
<entry></entry>
|
||||
<entry>a</entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
|
@ -259,6 +259,28 @@ for a pixel lie next to each other in memory.</para>
|
|||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-XRGB555X">
|
||||
<entry><constant>V4L2_PIX_FMT_XRGB555X</constant></entry>
|
||||
<entry>'XR15' | (1 << 31)</entry>
|
||||
<entry></entry>
|
||||
<entry>-</entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
<entry>r<subscript>3</subscript></entry>
|
||||
<entry>r<subscript>2</subscript></entry>
|
||||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>g<subscript>2</subscript></entry>
|
||||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
<entry>b<subscript>4</subscript></entry>
|
||||
<entry>b<subscript>3</subscript></entry>
|
||||
<entry>b<subscript>2</subscript></entry>
|
||||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-RGB565X">
|
||||
<entry><constant>V4L2_PIX_FMT_RGB565X</constant></entry>
|
||||
<entry>'RGBR'</entry>
|
||||
|
@ -464,7 +486,7 @@ for a pixel lie next to each other in memory.</para>
|
|||
</row>
|
||||
<row id="V4L2-PIX-FMT-ARGB32">
|
||||
<entry><constant>V4L2_PIX_FMT_ARGB32</constant></entry>
|
||||
<entry>'AX24'</entry>
|
||||
<entry>'BA24'</entry>
|
||||
<entry></entry>
|
||||
<entry>a<subscript>7</subscript></entry>
|
||||
<entry>a<subscript>6</subscript></entry>
|
||||
|
@ -800,6 +822,28 @@ image</title>
|
|||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-RGB555X">
|
||||
<entry><constant>V4L2_PIX_FMT_RGB555X</constant></entry>
|
||||
<entry>'RGBQ'</entry>
|
||||
<entry></entry>
|
||||
<entry>a</entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
<entry>r<subscript>3</subscript></entry>
|
||||
<entry>r<subscript>2</subscript></entry>
|
||||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>g<subscript>2</subscript></entry>
|
||||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
<entry>b<subscript>4</subscript></entry>
|
||||
<entry>b<subscript>3</subscript></entry>
|
||||
<entry>b<subscript>2</subscript></entry>
|
||||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-BGR32">
|
||||
<entry><constant>V4L2_PIX_FMT_BGR32</constant></entry>
|
||||
<entry>'BGR4'</entry>
|
||||
|
|
|
@ -76,21 +76,22 @@
|
|||
<entry></entry>
|
||||
<entry>&v4l2-event-vsync;</entry>
|
||||
<entry><structfield>vsync</structfield></entry>
|
||||
<entry>Event data for event V4L2_EVENT_VSYNC.
|
||||
<entry>Event data for event <constant>V4L2_EVENT_VSYNC</constant>.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry>&v4l2-event-ctrl;</entry>
|
||||
<entry><structfield>ctrl</structfield></entry>
|
||||
<entry>Event data for event V4L2_EVENT_CTRL.
|
||||
<entry>Event data for event <constant>V4L2_EVENT_CTRL</constant>.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry>&v4l2-event-frame-sync;</entry>
|
||||
<entry><structfield>frame_sync</structfield></entry>
|
||||
<entry>Event data for event V4L2_EVENT_FRAME_SYNC.</entry>
|
||||
<entry>Event data for event
|
||||
<constant>V4L2_EVENT_FRAME_SYNC</constant>.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
<funcdef>int <function>ioctl</function></funcdef>
|
||||
<paramdef>int <parameter>fd</parameter></paramdef>
|
||||
<paramdef>int <parameter>request</parameter></paramdef>
|
||||
<paramdef>const struct v4l2_edid *<parameter>argp</parameter></paramdef>
|
||||
<paramdef>struct v4l2_edid *<parameter>argp</parameter></paramdef>
|
||||
</funcprototype>
|
||||
</funcsynopsis>
|
||||
</refsynopsisdiv>
|
||||
|
@ -124,18 +124,18 @@
|
|||
maximum number of blocks as defined by the standard). When you set the EDID and
|
||||
<structfield>blocks</structfield> is 0, then the EDID is disabled or erased.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>__u8 *</entry>
|
||||
<entry><structfield>edid</structfield></entry>
|
||||
<entry>Pointer to memory that contains the EDID. The minimum size is
|
||||
<structfield>blocks</structfield> * 128.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>__u32</entry>
|
||||
<entry><structfield>reserved</structfield>[5]</entry>
|
||||
<entry>Reserved for future extensions. Applications and drivers must
|
||||
set the array to zero.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>__u8 *</entry>
|
||||
<entry><structfield>edid</structfield></entry>
|
||||
<entry>Pointer to memory that contains the EDID. The minimum size is
|
||||
<structfield>blocks</structfield> * 128.</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
|
|
|
@ -176,7 +176,7 @@
|
|||
</row>
|
||||
<row>
|
||||
<entry><constant>V4L2_EVENT_MOTION_DET</constant></entry>
|
||||
<entry>5</entry>
|
||||
<entry>6</entry>
|
||||
<entry>
|
||||
<para>Triggered whenever the motion detection state for one or more of the regions
|
||||
changes. This event has a &v4l2-event-motion-det; associated with it.</para>
|
||||
|
|
|
@ -2742,7 +2742,9 @@ struct _snd_pcm_runtime {
|
|||
|
||||
<para>
|
||||
Another note is that this callback is non-atomic
|
||||
(schedulable). This is important, because the
|
||||
(schedulable) as default, i.e. when no
|
||||
<structfield>nonatomic</structfield> flag set.
|
||||
This is important, because the
|
||||
<structfield>trigger</structfield> callback
|
||||
is atomic (non-schedulable). That is, mutexes or any
|
||||
schedule-related functions are not available in
|
||||
|
@ -2900,8 +2902,9 @@ struct _snd_pcm_runtime {
|
|||
</para>
|
||||
|
||||
<para>
|
||||
As mentioned, this callback is atomic. You cannot call
|
||||
functions which may sleep.
|
||||
As mentioned, this callback is atomic as default unless
|
||||
<structfield>nonatomic</structfield> flag set, and
|
||||
you cannot call functions which may sleep.
|
||||
The trigger callback should be as minimal as possible,
|
||||
just really triggering the DMA. The other stuff should be
|
||||
initialized hw_params and prepare callbacks properly
|
||||
|
@ -2936,7 +2939,7 @@ struct _snd_pcm_runtime {
|
|||
</para>
|
||||
|
||||
<para>
|
||||
This callback is also atomic.
|
||||
This callback is also atomic as default.
|
||||
</para>
|
||||
</section>
|
||||
|
||||
|
@ -2972,7 +2975,7 @@ struct _snd_pcm_runtime {
|
|||
is useful only for such a purpose.
|
||||
</para>
|
||||
<para>
|
||||
This callback is atomic.
|
||||
This callback is atomic as default.
|
||||
</para>
|
||||
</section>
|
||||
|
||||
|
@ -3175,6 +3178,21 @@ struct _snd_pcm_runtime {
|
|||
called with local interrupts disabled.
|
||||
</para>
|
||||
|
||||
<para>
|
||||
The recent changes in PCM core code, however, allow all PCM
|
||||
operations to be non-atomic. This assumes that the all caller
|
||||
sides are in non-atomic contexts. For example, the function
|
||||
<function>snd_pcm_period_elapsed()</function> is called
|
||||
typically from the interrupt handler. But, if you set up the
|
||||
driver to use a threaded interrupt handler, this call can be in
|
||||
non-atomic context, too. In such a case, you can set
|
||||
<structfield>nonatomic</structfield> filed of
|
||||
<structname>snd_pcm</structname> object after creating it.
|
||||
When this flag is set, mutex and rwsem are used internally in
|
||||
the PCM core instead of spin and rwlocks, so that you can call
|
||||
all PCM functions safely in a non-atomic context.
|
||||
</para>
|
||||
|
||||
</section>
|
||||
<section id="pcm-interface-constraints">
|
||||
<title>Constraints</title>
|
||||
|
|
|
@ -56,8 +56,20 @@ RCU_STALL_RAT_DELAY
|
|||
two jiffies. (This is a cpp macro, not a kernel configuration
|
||||
parameter.)
|
||||
|
||||
When a CPU detects that it is stalling, it will print a message similar
|
||||
to the following:
|
||||
rcupdate.rcu_task_stall_timeout
|
||||
|
||||
This boot/sysfs parameter controls the RCU-tasks stall warning
|
||||
interval. A value of zero or less suppresses RCU-tasks stall
|
||||
warnings. A positive value sets the stall-warning interval
|
||||
in jiffies. An RCU-tasks stall warning starts wtih the line:
|
||||
|
||||
INFO: rcu_tasks detected stalls on tasks:
|
||||
|
||||
And continues with the output of sched_show_task() for each
|
||||
task stalling the current RCU-tasks grace period.
|
||||
|
||||
For non-RCU-tasks flavors of RCU, when a CPU detects that it is stalling,
|
||||
it will print a message similar to the following:
|
||||
|
||||
INFO: rcu_sched_state detected stall on CPU 5 (t=2500 jiffies)
|
||||
|
||||
|
@ -174,8 +186,12 @@ o A CPU looping with preemption disabled. This condition can
|
|||
o A CPU looping with bottom halves disabled. This condition can
|
||||
result in RCU-sched and RCU-bh stalls.
|
||||
|
||||
o For !CONFIG_PREEMPT kernels, a CPU looping anywhere in the kernel
|
||||
without invoking schedule().
|
||||
o For !CONFIG_PREEMPT kernels, a CPU looping anywhere in the
|
||||
kernel without invoking schedule(). Note that cond_resched()
|
||||
does not necessarily prevent RCU CPU stall warnings. Therefore,
|
||||
if the looping in the kernel is really expected and desirable
|
||||
behavior, you might need to replace some of the cond_resched()
|
||||
calls with calls to cond_resched_rcu_qs().
|
||||
|
||||
o A CPU-bound real-time task in a CONFIG_PREEMPT kernel, which might
|
||||
happen to preempt a low-priority task in the middle of an RCU
|
||||
|
@ -208,11 +224,10 @@ o A hardware failure. This is quite unlikely, but has occurred
|
|||
This resulted in a series of RCU CPU stall warnings, eventually
|
||||
leading the realization that the CPU had failed.
|
||||
|
||||
The RCU, RCU-sched, and RCU-bh implementations have CPU stall warning.
|
||||
SRCU does not have its own CPU stall warnings, but its calls to
|
||||
synchronize_sched() will result in RCU-sched detecting RCU-sched-related
|
||||
CPU stalls. Please note that RCU only detects CPU stalls when there is
|
||||
a grace period in progress. No grace period, no CPU stall warnings.
|
||||
The RCU, RCU-sched, RCU-bh, and RCU-tasks implementations have CPU stall
|
||||
warning. Note that SRCU does -not- have CPU stall warnings. Please note
|
||||
that RCU only detects CPU stalls when there is a grace period in progress.
|
||||
No grace period, no CPU stall warnings.
|
||||
|
||||
To diagnose the cause of the stall, inspect the stack traces.
|
||||
The offending function will usually be near the top of the stack.
|
||||
|
|
|
@ -312,3 +312,30 @@ a code like this:
|
|||
|
||||
There are also devm_* versions of these functions which release the
|
||||
descriptors once the device is released.
|
||||
|
||||
MFD devices
|
||||
~~~~~~~~~~~
|
||||
The MFD devices register their children as platform devices. For the child
|
||||
devices there needs to be an ACPI handle that they can use to reference
|
||||
parts of the ACPI namespace that relate to them. In the Linux MFD subsystem
|
||||
we provide two ways:
|
||||
|
||||
o The children share the parent ACPI handle.
|
||||
o The MFD cell can specify the ACPI id of the device.
|
||||
|
||||
For the first case, the MFD drivers do not need to do anything. The
|
||||
resulting child platform device will have its ACPI_COMPANION() set to point
|
||||
to the parent device.
|
||||
|
||||
If the ACPI namespace has a device that we can match using an ACPI id,
|
||||
the id should be set like:
|
||||
|
||||
static struct mfd_cell my_subdevice_cell = {
|
||||
.name = "my_subdevice",
|
||||
/* set the resources relative to the parent */
|
||||
.acpi_pnpid = "XYZ0001",
|
||||
};
|
||||
|
||||
The ACPI id "XYZ0001" is then used to lookup an ACPI device directly under
|
||||
the MFD device and if found, that ACPI companion device is bound to the
|
||||
resulting child platform device.
|
||||
|
|
|
@ -15,39 +15,50 @@ First you must mount binfmt_misc:
|
|||
mount binfmt_misc -t binfmt_misc /proc/sys/fs/binfmt_misc
|
||||
|
||||
To actually register a new binary type, you have to set up a string looking like
|
||||
:name:type:offset:magic:mask:interpreter:flags (where you can choose the ':' upon
|
||||
your needs) and echo it to /proc/sys/fs/binfmt_misc/register.
|
||||
:name:type:offset:magic:mask:interpreter:flags (where you can choose the ':'
|
||||
upon your needs) and echo it to /proc/sys/fs/binfmt_misc/register.
|
||||
|
||||
Here is what the fields mean:
|
||||
- 'name' is an identifier string. A new /proc file will be created with this
|
||||
name below /proc/sys/fs/binfmt_misc
|
||||
name below /proc/sys/fs/binfmt_misc; cannot contain slashes '/' for obvious
|
||||
reasons.
|
||||
- 'type' is the type of recognition. Give 'M' for magic and 'E' for extension.
|
||||
- 'offset' is the offset of the magic/mask in the file, counted in bytes. This
|
||||
defaults to 0 if you omit it (i.e. you write ':name:type::magic...')
|
||||
defaults to 0 if you omit it (i.e. you write ':name:type::magic...'). Ignored
|
||||
when using filename extension matching.
|
||||
- 'magic' is the byte sequence binfmt_misc is matching for. The magic string
|
||||
may contain hex-encoded characters like \x0a or \xA4. In a shell environment
|
||||
you will have to write \\x0a to prevent the shell from eating your \.
|
||||
may contain hex-encoded characters like \x0a or \xA4. Note that you must
|
||||
escape any NUL bytes; parsing halts at the first one. In a shell environment
|
||||
you might have to write \\x0a to prevent the shell from eating your \.
|
||||
If you chose filename extension matching, this is the extension to be
|
||||
recognised (without the '.', the \x0a specials are not allowed). Extension
|
||||
matching is case sensitive!
|
||||
matching is case sensitive, and slashes '/' are not allowed!
|
||||
- 'mask' is an (optional, defaults to all 0xff) mask. You can mask out some
|
||||
bits from matching by supplying a string like magic and as long as magic.
|
||||
The mask is anded with the byte sequence of the file.
|
||||
The mask is anded with the byte sequence of the file. Note that you must
|
||||
escape any NUL bytes; parsing halts at the first one. Ignored when using
|
||||
filename extension matching.
|
||||
- 'interpreter' is the program that should be invoked with the binary as first
|
||||
argument (specify the full path)
|
||||
- 'flags' is an optional field that controls several aspects of the invocation
|
||||
of the interpreter. It is a string of capital letters, each controls a certain
|
||||
aspect. The following flags are supported -
|
||||
'P' - preserve-argv[0]. Legacy behavior of binfmt_misc is to overwrite the
|
||||
original argv[0] with the full path to the binary. When this flag is
|
||||
included, binfmt_misc will add an argument to the argument vector for
|
||||
this purpose, thus preserving the original argv[0].
|
||||
of the interpreter. It is a string of capital letters, each controls a
|
||||
certain aspect. The following flags are supported -
|
||||
'P' - preserve-argv[0]. Legacy behavior of binfmt_misc is to overwrite
|
||||
the original argv[0] with the full path to the binary. When this
|
||||
flag is included, binfmt_misc will add an argument to the argument
|
||||
vector for this purpose, thus preserving the original argv[0].
|
||||
e.g. If your interp is set to /bin/foo and you run `blah` (which is
|
||||
in /usr/local/bin), then the kernel will execute /bin/foo with
|
||||
argv[] set to ["/bin/foo", "/usr/local/bin/blah", "blah"]. The
|
||||
interp has to be aware of this so it can execute /usr/local/bin/blah
|
||||
with argv[] set to ["blah"].
|
||||
'O' - open-binary. Legacy behavior of binfmt_misc is to pass the full path
|
||||
of the binary to the interpreter as an argument. When this flag is
|
||||
included, binfmt_misc will open the file for reading and pass its
|
||||
descriptor as an argument, instead of the full path, thus allowing
|
||||
the interpreter to execute non-readable binaries. This feature should
|
||||
be used with care - the interpreter has to be trusted not to emit
|
||||
the contents of the non-readable binary.
|
||||
the interpreter to execute non-readable binaries. This feature
|
||||
should be used with care - the interpreter has to be trusted not to
|
||||
emit the contents of the non-readable binary.
|
||||
'C' - credentials. Currently, the behavior of binfmt_misc is to calculate
|
||||
the credentials and security token of the new process according to
|
||||
the interpreter. When this flag is included, these attributes are
|
||||
|
@ -58,7 +69,7 @@ Here is what the fields mean:
|
|||
|
||||
|
||||
There are some restrictions:
|
||||
- the whole register string may not exceed 255 characters
|
||||
- the whole register string may not exceed 1920 characters
|
||||
- the magic must reside in the first 128 bytes of the file, i.e.
|
||||
offset+size(magic) has to be less than 128
|
||||
- the interpreter string may not exceed 127 characters
|
||||
|
@ -110,7 +121,4 @@ passes it the full filename (or the file descriptor) to use. Using $PATH can
|
|||
cause unexpected behaviour and can be a security hazard.
|
||||
|
||||
|
||||
There is a web page about binfmt_misc at
|
||||
http://www.tat.physik.uni-tuebingen.de
|
||||
|
||||
Richard Günther <rguenth@tat.physik.uni-tuebingen.de>
|
||||
|
|
|
@ -129,11 +129,11 @@ interface for this is being worked on.
|
|||
4.1 BIO
|
||||
|
||||
The data integrity patches add a new field to struct bio when
|
||||
CONFIG_BLK_DEV_INTEGRITY is enabled. bio->bi_integrity is a pointer
|
||||
to a struct bip which contains the bio integrity payload. Essentially
|
||||
a bip is a trimmed down struct bio which holds a bio_vec containing
|
||||
the integrity metadata and the required housekeeping information (bvec
|
||||
pool, vector count, etc.)
|
||||
CONFIG_BLK_DEV_INTEGRITY is enabled. bio_integrity(bio) returns a
|
||||
pointer to a struct bip which contains the bio integrity payload.
|
||||
Essentially a bip is a trimmed down struct bio which holds a bio_vec
|
||||
containing the integrity metadata and the required housekeeping
|
||||
information (bvec pool, vector count, etc.)
|
||||
|
||||
A kernel subsystem can enable data integrity protection on a bio by
|
||||
calling bio_integrity_alloc(bio). This will allocate and attach the
|
||||
|
@ -192,16 +192,6 @@ will require extra work due to the application tag.
|
|||
supported by the block device.
|
||||
|
||||
|
||||
int bdev_integrity_enabled(block_device, int rw);
|
||||
|
||||
bdev_integrity_enabled() will return 1 if the block device
|
||||
supports integrity metadata transfer for the data direction
|
||||
specified in 'rw'.
|
||||
|
||||
bdev_integrity_enabled() honors the write_generate and
|
||||
read_verify flags in sysfs and will respond accordingly.
|
||||
|
||||
|
||||
int bio_integrity_prep(bio);
|
||||
|
||||
To generate IMD for WRITE and to set up buffers for READ, the
|
||||
|
@ -216,36 +206,6 @@ will require extra work due to the application tag.
|
|||
bio_integrity_enabled() returned 1.
|
||||
|
||||
|
||||
int bio_integrity_tag_size(bio);
|
||||
|
||||
If the filesystem wants to use the application tag space it will
|
||||
first have to find out how much storage space is available.
|
||||
Because tag space is generally limited (usually 2 bytes per
|
||||
sector regardless of sector size), the integrity framework
|
||||
supports interleaving the information between the sectors in an
|
||||
I/O.
|
||||
|
||||
Filesystems can call bio_integrity_tag_size(bio) to find out how
|
||||
many bytes of storage are available for that particular bio.
|
||||
|
||||
Another option is bdev_get_tag_size(block_device) which will
|
||||
return the number of available bytes per hardware sector.
|
||||
|
||||
|
||||
int bio_integrity_set_tag(bio, void *tag_buf, len);
|
||||
|
||||
After a successful return from bio_integrity_prep(),
|
||||
bio_integrity_set_tag() can be used to attach an opaque tag
|
||||
buffer to a bio. Obviously this only makes sense if the I/O is
|
||||
a WRITE.
|
||||
|
||||
|
||||
int bio_integrity_get_tag(bio, void *tag_buf, len);
|
||||
|
||||
Similarly, at READ I/O completion time the filesystem can
|
||||
retrieve the tag buffer using bio_integrity_get_tag().
|
||||
|
||||
|
||||
5.3 PASSING EXISTING INTEGRITY METADATA
|
||||
|
||||
Filesystems that either generate their own integrity metadata or
|
||||
|
@ -298,8 +258,6 @@ will require extra work due to the application tag.
|
|||
.name = "STANDARDSBODY-TYPE-VARIANT-CSUM",
|
||||
.generate_fn = my_generate_fn,
|
||||
.verify_fn = my_verify_fn,
|
||||
.get_tag_fn = my_get_tag_fn,
|
||||
.set_tag_fn = my_set_tag_fn,
|
||||
.tuple_size = sizeof(struct my_tuple_size),
|
||||
.tag_size = <tag bytes per hw sector>,
|
||||
};
|
||||
|
@ -321,7 +279,5 @@ will require extra work due to the application tag.
|
|||
are available per hardware sector. For DIF this is either 2 or
|
||||
0 depending on the value of the Control Mode Page ATO bit.
|
||||
|
||||
See 6.2 for a description of get_tag_fn and set_tag_fn.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
2007-12-24 Martin K. Petersen <martin.petersen@oracle.com>
|
||||
|
|
|
@ -74,14 +74,30 @@ There is little point creating a zram of greater than twice the size of memory
|
|||
since we expect a 2:1 compression ratio. Note that zram uses about 0.1% of the
|
||||
size of the disk when not in use so a huge zram is wasteful.
|
||||
|
||||
5) Activate:
|
||||
5) Set memory limit: Optional
|
||||
Set memory limit by writing the value to sysfs node 'mem_limit'.
|
||||
The value can be either in bytes or you can use mem suffixes.
|
||||
In addition, you could change the value in runtime.
|
||||
Examples:
|
||||
# limit /dev/zram0 with 50MB memory
|
||||
echo $((50*1024*1024)) > /sys/block/zram0/mem_limit
|
||||
|
||||
# Using mem suffixes
|
||||
echo 256K > /sys/block/zram0/mem_limit
|
||||
echo 512M > /sys/block/zram0/mem_limit
|
||||
echo 1G > /sys/block/zram0/mem_limit
|
||||
|
||||
# To disable memory limit
|
||||
echo 0 > /sys/block/zram0/mem_limit
|
||||
|
||||
6) Activate:
|
||||
mkswap /dev/zram0
|
||||
swapon /dev/zram0
|
||||
|
||||
mkfs.ext4 /dev/zram1
|
||||
mount /dev/zram1 /tmp
|
||||
|
||||
6) Stats:
|
||||
7) Stats:
|
||||
Per-device statistics are exported as various nodes under
|
||||
/sys/block/zram<id>/
|
||||
disksize
|
||||
|
@ -95,12 +111,13 @@ size of the disk when not in use so a huge zram is wasteful.
|
|||
orig_data_size
|
||||
compr_data_size
|
||||
mem_used_total
|
||||
mem_used_max
|
||||
|
||||
7) Deactivate:
|
||||
8) Deactivate:
|
||||
swapoff /dev/zram0
|
||||
umount /dev/zram1
|
||||
|
||||
8) Reset:
|
||||
9) Reset:
|
||||
Write any positive value to 'reset' sysfs node
|
||||
echo 1 > /sys/block/zram0/reset
|
||||
echo 1 > /sys/block/zram1/reset
|
||||
|
|
|
@ -8,6 +8,8 @@ Required Properties:
|
|||
* samsung,exynos4210-pd - for exynos4210 type power domain.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #power-domain-cells: number of cells in power domain specifier;
|
||||
must be 0.
|
||||
|
||||
Optional Properties:
|
||||
- clocks: List of clock handles. The parent clocks of the input clocks to the
|
||||
|
@ -29,6 +31,7 @@ Example:
|
|||
lcd0: power-domain-lcd0 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10023C00 0x10>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
mfc_pd: power-domain@10044060 {
|
||||
|
@ -37,12 +40,8 @@ Example:
|
|||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
|
||||
<&clock CLK_MOUT_USER_ACLK333>;
|
||||
clock-names = "oscclk", "pclk0", "clk0";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
Example of the node using power domain:
|
||||
|
||||
node {
|
||||
/* ... */
|
||||
samsung,power-domain = <&lcd0>;
|
||||
/* ... */
|
||||
};
|
||||
See Documentation/devicetree/bindings/power/power_domain.txt for description
|
||||
of consumer-side bindings.
|
||||
|
|
48
Documentation/devicetree/bindings/ata/qcom-sata.txt
Normal file
48
Documentation/devicetree/bindings/ata/qcom-sata.txt
Normal file
|
@ -0,0 +1,48 @@
|
|||
* Qualcomm AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, must contain "generic-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
- phys : Must contain exactly one entry as specified
|
||||
in phy-bindings.txt
|
||||
- phy-names : Must be "sata-phy"
|
||||
|
||||
Required properties for "qcom,ipq806x-ahci" compatible:
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Shall be:
|
||||
"slave_iface" - Fabric port AHB clock for SATA
|
||||
"iface" - AHB clock
|
||||
"core" - core clock
|
||||
"rxoob" - RX out-of-band clock
|
||||
"pmalive" - Power Module Alive clock
|
||||
- assigned-clocks : Shall be:
|
||||
SATA_RXOOB_CLK
|
||||
SATA_PMALIVE_CLK
|
||||
- assigned-clock-rates : Shall be:
|
||||
100Mhz (100000000) for SATA_RXOOB_CLK
|
||||
100Mhz (100000000) for SATA_PMALIVE_CLK
|
||||
|
||||
Example:
|
||||
sata@29000000 {
|
||||
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
||||
reg = <0x29000000 0x180>;
|
||||
|
||||
interrupts = <0 209 0x0>;
|
||||
|
||||
clocks = <&gcc SFAB_SATA_S_H_CLK>,
|
||||
<&gcc SATA_H_CLK>,
|
||||
<&gcc SATA_A_CLK>,
|
||||
<&gcc SATA_RXOOB_CLK>,
|
||||
<&gcc SATA_PMALIVE_CLK>;
|
||||
clock-names = "slave_iface", "iface", "core",
|
||||
"rxoob", "pmalive";
|
||||
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
|
||||
assigned-clock-rates = <100000000>, <100000000>;
|
||||
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
|
@ -8,6 +8,11 @@ Required properties:
|
|||
|
||||
The cores on the AXI bus are automatically detected by bcma with the
|
||||
memory ranges they are using and they get registered afterwards.
|
||||
Automatic detection of the IRQ number is not working on
|
||||
BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
|
||||
them manually through device tree. Use an interrupt-map to specify the
|
||||
IRQ used by the devices on the bus. The first address is just an index,
|
||||
because we do not have any special register.
|
||||
|
||||
The top-level axi bus may contain children representing attached cores
|
||||
(devices). This is needed since some hardware details can't be auto
|
||||
|
@ -22,6 +27,22 @@ Example:
|
|||
ranges = <0x00000000 0x18000000 0x00100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0x000fffff 0xffff>;
|
||||
interrupt-map =
|
||||
/* Ethernet Controller 0 */
|
||||
<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
/* Ethernet Controller 1 */
|
||||
<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/* PCIe Controller 0 */
|
||||
<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
chipcommon {
|
||||
reg = <0x00000000 0x1000>;
|
||||
|
|
|
@ -7,6 +7,8 @@ Required Properties:
|
|||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
|
||||
- "samsung,exynos3250-cmu-dmc" - controller compatible with
|
||||
Exynos3250 SoC for Dynamic Memory Controller domain.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in
|
|||
dt-bindings/clock/exynos3250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
Example 1: Examples of clock controller nodes are listed below.
|
||||
|
||||
cmu: clock-controller@10030000 {
|
||||
compatible = "samsung,exynos3250-cmu";
|
||||
|
@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below.
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_dmc: clock-controller@105C0000 {
|
||||
compatible = "samsung,exynos3250-cmu-dmc";
|
||||
reg = <0x105C0000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
|
21
Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
Normal file
21
Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
Normal file
|
@ -0,0 +1,21 @@
|
|||
Binding for simple gpio gated clock.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "gpio-gate-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- enable-gpios : GPIO reference for enabling and disabling the clock.
|
||||
|
||||
Optional properties:
|
||||
- clocks: Maximum of one parent clock is supported.
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "gpio-gate-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
|
@ -9,13 +9,21 @@ The MAX77686 contains three 32.768khz clock outputs that can be controlled
|
|||
Following properties should be presend in main device node of the MFD chip.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: simple one-cell clock specifier format is used, where the
|
||||
only cell is used as an index of the clock inside the provider. Following
|
||||
indices are allowed:
|
||||
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock binding.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Following indices are allowed:
|
||||
- 0: 32khz_ap clock,
|
||||
- 1: 32khz_cp clock,
|
||||
- 2: 32khz_pmic clock.
|
||||
|
||||
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
|
||||
header and can be used in device tree sources.
|
||||
|
||||
Example: Node of the MFD chip
|
||||
|
||||
max77686: max77686@09 {
|
||||
|
@ -34,5 +42,5 @@ Example: Clock consumer node
|
|||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77686 2>;
|
||||
clocks = <&max77686 MAX77686_CLK_PMIC>;
|
||||
};
|
||||
|
|
44
Documentation/devicetree/bindings/clock/maxim,max77802.txt
Normal file
44
Documentation/devicetree/bindings/clock/maxim,max77802.txt
Normal file
|
@ -0,0 +1,44 @@
|
|||
Binding for Maxim MAX77802 32k clock generator block
|
||||
|
||||
This is a part of device tree bindings of MAX77802 multi-function device.
|
||||
More information can be found in bindings/mfd/max77802.txt file.
|
||||
|
||||
The MAX77802 contains two 32.768khz clock outputs that can be controlled
|
||||
(gated/ungated) over I2C.
|
||||
|
||||
Following properties should be present in main device node of the MFD chip.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: From common clock binding; shall be set to 1.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock binding.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Following indices are allowed:
|
||||
- 0: 32khz_ap clock,
|
||||
- 1: 32khz_cp clock.
|
||||
|
||||
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
|
||||
header and can be used in device tree sources.
|
||||
|
||||
Example: Node of the MFD chip
|
||||
|
||||
max77802: max77802@09 {
|
||||
compatible = "maxim,max77802";
|
||||
interrupt-parent = <&wakeup_eint>;
|
||||
interrupts = <26 0>;
|
||||
reg = <0x09>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
||||
Example: Clock consumer node
|
||||
|
||||
foo@0 {
|
||||
compatible = "bar,foo";
|
||||
/* ... */
|
||||
clock-names = "my-clock";
|
||||
clocks = <&max77802 MAX77802_CLK_32K_AP>;
|
||||
};
|
16
Documentation/devicetree/bindings/clock/pxa-clock.txt
Normal file
16
Documentation/devicetree/bindings/clock/pxa-clock.txt
Normal file
|
@ -0,0 +1,16 @@
|
|||
* Clock bindings for Marvell PXA chips
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pxa-clocks"
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell (see include/.../pxa-clock.h).
|
||||
|
||||
Examples:
|
||||
|
||||
pxa2xx_clks: pxa2xx_clks@41300004 {
|
||||
compatible = "marvell,pxa-clocks";
|
||||
#clock-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
|
@ -15,6 +15,7 @@ Required Properties:
|
|||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
|
||||
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
|
||||
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
|
||||
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
|
||||
- reg: Base address and length of the I/O mapped registers used by the MSTP
|
||||
|
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- compatible: Must be one of
|
||||
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||||
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||||
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||||
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
|
|
@ -46,7 +46,11 @@ Required properties:
|
|||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
|
||||
"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
Generic CPU0 cpufreq driver
|
||||
Generic cpufreq driver
|
||||
|
||||
It is a generic cpufreq driver for CPU0 frequency management. It
|
||||
supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
|
||||
systems which share clock and voltage across all CPUs.
|
||||
It is a generic DT based cpufreq driver for frequency management. It supports
|
||||
both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
|
||||
clock and voltage across all CPUs.
|
||||
|
||||
Both required and optional properties listed below must be defined
|
||||
under node /cpus/cpu@0.
|
62
Documentation/devicetree/bindings/dma/qcom_adm.txt
Normal file
62
Documentation/devicetree/bindings/dma/qcom_adm.txt
Normal file
|
@ -0,0 +1,62 @@
|
|||
QCOM ADM DMA Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
|
||||
- reg: Address range for DMA registers
|
||||
- interrupts: Should contain one interrupt shared by all channels
|
||||
- #dma-cells: must be <2>. First cell denotes the channel number. Second cell
|
||||
denotes CRCI (client rate control interface) flow control assignment.
|
||||
- clocks: Should contain the core clock and interface clock.
|
||||
- clock-names: Must contain "core" for the core clock and "iface" for the
|
||||
interface clock.
|
||||
- resets: Must contain an entry for each entry in reset names.
|
||||
- reset-names: Must include the following entries:
|
||||
- clk
|
||||
- c0
|
||||
- c1
|
||||
- c2
|
||||
- qcom,ee: indicates the security domain identifier used in the secure world.
|
||||
|
||||
Example:
|
||||
adm_dma: dma@18300000 {
|
||||
compatible = "qcom,adm";
|
||||
reg = <0x18300000 0x100000>;
|
||||
interrupts = <0 170 0>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
|
||||
resets = <&gcc ADM0_RESET>,
|
||||
<&gcc ADM0_C0_RESET>,
|
||||
<&gcc ADM0_C1_RESET>,
|
||||
<&gcc ADM0_C2_RESET>;
|
||||
reset-names = "clk", "c0", "c1", "c2";
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
DMA clients must use the format descripted in the dma.txt file, using a three
|
||||
cell specifier for each channel.
|
||||
|
||||
Each dmas request consists of 3 cells:
|
||||
1. phandle pointing to the DMA controller
|
||||
2. channel number
|
||||
3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
|
||||
The CRCI is used for flow control. It identifies the peripheral device that
|
||||
is the source/destination for the transferred data.
|
||||
|
||||
Example:
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
dmas = <&adm_dma 6 9>,
|
||||
<&adm_dma 5 10>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
65
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
Normal file
65
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
Normal file
|
@ -0,0 +1,65 @@
|
|||
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
|
||||
target devices. It can be configured to have one channel or two channels.
|
||||
If configured as two channels, one is to transmit to the device and another
|
||||
is to receive from the device.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-dma-1.00.a"
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- dma-channel child node: Should have atleast one channel and can have upto
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells whether configured for Scatter-mode in
|
||||
the hardware.
|
||||
|
||||
Required child node properties:
|
||||
- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
|
||||
"xlnx,axi-dma-s2mm-channel".
|
||||
- interrupts: Should contain per channel DMA interrupts.
|
||||
- xlnx,datawidth: Should contain the stream data width, take values
|
||||
{32,64...1024}.
|
||||
|
||||
Option child node properties:
|
||||
- xlnx,include-dre: Tells whether hardware is configured for Data
|
||||
Realignment Engine.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
axi_dma_0: axidma@40400000 {
|
||||
compatible = "xlnx,axi-dma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40400000 0x10000 >;
|
||||
dma-channel@40400000 {
|
||||
compatible = "xlnx,axi-dma-mm2s-channel";
|
||||
interrupts = < 0 59 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
dma-channel@40400030 {
|
||||
compatible = "xlnx,axi-dma-s2mm-channel";
|
||||
interrupts = < 0 58 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
dmatest_0: dmatest@0 {
|
||||
compatible ="xlnx,axi-dma-test-1.00.a";
|
||||
dmas = <&axi_dma_0 0
|
||||
&axi_dma_0 1>;
|
||||
dma-names = "dma0", "dma1";
|
||||
} ;
|
|
@ -18,6 +18,10 @@ Required properties:
|
|||
Documentation/devicetree/bindings/video/display-timing.txt for display
|
||||
timing binding details.
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
- enable-gpios: GPIO pin to enable or disable the panel
|
||||
|
||||
Recommended properties:
|
||||
- pinctrl-names, pinctrl-0: the pincontrol settings to configure
|
||||
muxing properly for pins that connect to TFP410 device
|
||||
|
@ -29,6 +33,9 @@ Example:
|
|||
compatible = "ti,tilcdc,panel";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bone_lcd3_cape_lcd_pins>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio3 19 0>;
|
||||
|
||||
panel-info {
|
||||
ac-bias = <255>;
|
||||
ac-bias-intrpt = <0>;
|
||||
|
|
39
Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
Normal file
39
Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
Normal file
|
@ -0,0 +1,39 @@
|
|||
Keystone 2 DSP GPIO controller bindings
|
||||
|
||||
HOST OS userland running on ARM can send interrupts to DSP cores using
|
||||
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
|
||||
This is one of the component used by the IPC mechanism used on Keystone SOCs.
|
||||
|
||||
For example TCI6638K2K SoC has 8 DSP GPIO controllers:
|
||||
- 8 for C66x CorePacx CPUs 0-7
|
||||
|
||||
Keystone 2 DSP GPIO controller has specific features:
|
||||
- each GPIO can be configured only as output pin;
|
||||
- setting GPIO value to 1 causes IRQ generation on target DSP core;
|
||||
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
|
||||
pending.
|
||||
|
||||
Required Properties:
|
||||
- compatible: should be "ti,keystone-dsp-gpio"
|
||||
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
|
||||
access device state control registers and the offset of device's specific
|
||||
registers within device state control registers range.
|
||||
- gpio-controller: Marks the device node as a gpio controller.
|
||||
- #gpio-cells: Should be 2.
|
||||
|
||||
Please refer to gpio.txt in this directory for details of the common GPIO
|
||||
bindings used by client devices.
|
||||
|
||||
Example:
|
||||
dspgpio0: keystone_dsp_gpio@02620240 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
ti,syscon-dev = <&devctrl 0x240>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
dsp0: dsp0 {
|
||||
compatible = "linux,rproc-user";
|
||||
...
|
||||
kick-gpio = <&dspgpio0 27>;
|
||||
};
|
39
Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
Normal file
39
Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
Normal file
|
@ -0,0 +1,39 @@
|
|||
* NXP PCA953x I2C GPIO multiplexer
|
||||
|
||||
Required properties:
|
||||
- compatible: Has to contain one of the following:
|
||||
nxp,pca9505
|
||||
nxp,pca9534
|
||||
nxp,pca9535
|
||||
nxp,pca9536
|
||||
nxp,pca9537
|
||||
nxp,pca9538
|
||||
nxp,pca9539
|
||||
nxp,pca9554
|
||||
nxp,pca9555
|
||||
nxp,pca9556
|
||||
nxp,pca9557
|
||||
nxp,pca9574
|
||||
nxp,pca9575
|
||||
nxp,pca9698
|
||||
maxim,max7310
|
||||
maxim,max7312
|
||||
maxim,max7313
|
||||
maxim,max7315
|
||||
ti,pca6107
|
||||
ti,tca6408
|
||||
ti,tca6416
|
||||
ti,tca6424
|
||||
exar,xra1202
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
gpio@20 {
|
||||
compatible = "nxp,pca9505";
|
||||
reg = <0x20>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pca9505>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
54
Documentation/devicetree/bindings/gpio/gpio-restart.txt
Normal file
54
Documentation/devicetree/bindings/gpio/gpio-restart.txt
Normal file
|
@ -0,0 +1,54 @@
|
|||
Drive a GPIO line that can be used to restart the system from a restart
|
||||
handler.
|
||||
|
||||
This binding supports level and edge triggered reset. At driver load
|
||||
time, the driver will request the given gpio line and install a restart
|
||||
handler. If the optional properties 'open-source' is not found, the GPIO line
|
||||
will be driven in the inactive state. Otherwise its not driven until
|
||||
the restart is initiated.
|
||||
|
||||
When the system is restarted, the restart handler will be invoked in
|
||||
priority order. The gpio is configured as an output, and driven active,
|
||||
triggering a level triggered reset condition. This will also cause an
|
||||
inactive->active edge condition, triggering positive edge triggered
|
||||
reset. After a delay specified by active-delay, the GPIO is set to
|
||||
inactive, thus causing an active->inactive edge, triggering negative edge
|
||||
triggered reset. After a delay specified by inactive-delay, the GPIO
|
||||
is driven active again. After a delay specified by wait-delay, the
|
||||
restart handler completes allowing other restart handlers to be attempted.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "gpio-restart".
|
||||
- gpios : The GPIO to set high/low, see "gpios property" in
|
||||
Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
|
||||
low to reset the board set it to "Active Low", otherwise set
|
||||
gpio to "Active High".
|
||||
|
||||
Optional properties:
|
||||
- open-source : Treat the GPIO as being open source and defer driving
|
||||
it to when the restart is initiated. If this optional property is not
|
||||
specified, the GPIO is initialized as an output in its inactive state.
|
||||
- priority : A priority ranging from 0 to 255 (default 128) according to
|
||||
the following guidelines:
|
||||
0: Restart handler of last resort, with limited restart
|
||||
capabilities
|
||||
128: Default restart handler; use if no other restart handler is
|
||||
expected to be available, and/or if restart functionality is
|
||||
sufficient to restart the entire system
|
||||
255: Highest priority restart handler, will preempt all other
|
||||
restart handlers
|
||||
- active-delay: Delay (default 100) to wait after driving gpio active [ms]
|
||||
- inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms]
|
||||
- wait-delay: Delay (default 3000) to wait after completing restart
|
||||
sequence [ms]
|
||||
|
||||
Examples:
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 4 0>;
|
||||
priority = <128>;
|
||||
active-delay = <100>;
|
||||
inactive-delay = <100>;
|
||||
wait-delay = <3000>;
|
||||
};
|
22
Documentation/devicetree/bindings/gpio/gpio-xgene.txt
Normal file
22
Documentation/devicetree/bindings/gpio/gpio-xgene.txt
Normal file
|
@ -0,0 +1,22 @@
|
|||
APM X-Gene SoC GPIO controller bindings
|
||||
|
||||
This is a gpio controller that is part of the flash controller.
|
||||
This gpio controller controls a total of 48 gpios.
|
||||
|
||||
Required properties:
|
||||
- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
|
||||
- reg: Physical base address and size of the controller's registers
|
||||
- #gpio-cells: Should be two.
|
||||
- first cell is the pin number
|
||||
- second cell is used to specify the gpio polarity:
|
||||
0 = active high
|
||||
1 = active low
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
|
||||
Example:
|
||||
gpio0: gpio0@1701c000 {
|
||||
compatible = "apm,xgene-gpio";
|
||||
reg = <0x0 0x1701c000 0x0 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
|
@ -19,7 +19,7 @@ Required properties:
|
|||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
- #gpio-cells : Should be one. It is the pin number.
|
||||
|
||||
Example:
|
||||
Example for a MMP platform:
|
||||
|
||||
gpio: gpio@d4019000 {
|
||||
compatible = "marvell,mmp-gpio";
|
||||
|
@ -32,6 +32,19 @@ Example:
|
|||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
Example for a PXA3xx platform:
|
||||
|
||||
gpio: gpio@40e00000 {
|
||||
compatible = "intel,pxa3xx-gpio";
|
||||
reg = <0x40e00000 0x10000>;
|
||||
interrupt-names = "gpio0", "gpio1", "gpio_mux";
|
||||
interrupts = <8 9 10>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
};
|
||||
|
||||
* Marvell Orion GPIO Controller
|
||||
|
||||
Required properties:
|
||||
|
|
|
@ -25,6 +25,9 @@ Requires node properties:
|
|||
- "io-channels" Channel node of ADC to be used for
|
||||
conversion.
|
||||
|
||||
Optional node properties:
|
||||
- "#thermal-sensor-cells" Used to expose itself to thermal fw.
|
||||
|
||||
Read more about iio bindings at
|
||||
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
||||
|
||||
|
|
30
Documentation/devicetree/bindings/i2c/i2c-axxia.txt
Normal file
30
Documentation/devicetree/bindings/i2c/i2c-axxia.txt
Normal file
|
@ -0,0 +1,30 @@
|
|||
LSI Axxia I2C
|
||||
|
||||
Required properties :
|
||||
- compatible : Must be "lsi,api2c"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : the interrupt specifier
|
||||
- #address-cells : Must be <1>;
|
||||
- #size-cells : Must be <0>;
|
||||
- clock-names : Must contain "i2c".
|
||||
- clocks: Must contain an entry for each name in clock-names. See the common
|
||||
clock bindings.
|
||||
|
||||
Optional properties :
|
||||
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used. As only Normal and Fast modes
|
||||
are supported, possible values are 100000 and 400000.
|
||||
|
||||
Example :
|
||||
|
||||
i2c@02010084000 {
|
||||
compatible = "lsi,api2c";
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x20 0x10084000 0x00 0x1000>;
|
||||
interrupts = <0 19 4>;
|
||||
clocks = <&clk_per>;
|
||||
clock-names = "i2c";
|
||||
clock-frequency = <400000>;
|
||||
};
|
|
@ -12,6 +12,8 @@ Required properties:
|
|||
on Exynos5250 and Exynos5420 SoCs.
|
||||
-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos5260 SoCs.
|
||||
-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos7 SoCs.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
|
24
Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
Normal file
24
Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt
Normal file
|
@ -0,0 +1,24 @@
|
|||
I2C for Hisilicon hix5hd2 chipset platform
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "hisilicon,hix5hd2-i2c"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- clocks: phandles to input clocks.
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
|
||||
- Child nodes conforming to i2c bus binding
|
||||
|
||||
Examples:
|
||||
I2C0@f8b10000 {
|
||||
compatible = "hisilicon,hix5hd2-i2c";
|
||||
reg = <0xf8b10000 0x1000>;
|
||||
interrupts = <0 38 4>;
|
||||
clocks = <&clock HIX5HD2_I2C0_RST>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
}
|
18
Documentation/devicetree/bindings/i2c/ti,bq32k.txt
Normal file
18
Documentation/devicetree/bindings/i2c/ti,bq32k.txt
Normal file
|
@ -0,0 +1,18 @@
|
|||
* TI BQ32000 I2C Serial Real-Time Clock
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "ti,bq32000".
|
||||
- reg: I2C address for chip
|
||||
|
||||
Optional properties:
|
||||
- trickle-resistor-ohms : Selected resistor for trickle charger
|
||||
Values usable are 1120 and 20180
|
||||
Should be given if trickle charger should be enabled
|
||||
- trickle-diode-disable : Do not use internal trickle charger diode
|
||||
Should be given if internal trickle charger diode should be disabled
|
||||
Example:
|
||||
bq32000: rtc@68 {
|
||||
compatible = "ti,bq32000";
|
||||
trickle-resistor-ohms = <1120>;
|
||||
reg = <0x68>;
|
||||
};
|
|
@ -35,7 +35,6 @@ catalyst,24c32 i2c serial eeprom
|
|||
cirrus,cs42l51 Cirrus Logic CS42L51 audio codec
|
||||
dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock
|
||||
dallas,ds1338 I2C RTC with 56-Byte NV RAM
|
||||
dallas,ds1339 I2C Serial Real-Time Clock
|
||||
dallas,ds1340 I2C RTC with Trickle Charger
|
||||
dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
|
||||
dallas,ds1631 High-Precision Digital Thermometer
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
Required properties:
|
||||
- compatible: Should be "atmel,<chip>-aic"
|
||||
<chip> can be "at91rm9200" or "sama5d3"
|
||||
<chip> can be "at91rm9200", "sama5d3" or "sama5d4"
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- interrupt-parent: For single AIC system, it is an empty property.
|
||||
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
|
||||
|
|
|
@ -0,0 +1,86 @@
|
|||
Broadcom BCM7120-style Level 2 interrupt controller
|
||||
|
||||
This interrupt controller hardware is a second level interrupt controller that
|
||||
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
|
||||
platforms. It can be found on BCM7xxx products starting with BCM7120.
|
||||
|
||||
Such an interrupt controller has the following hardware design:
|
||||
|
||||
- outputs multiple interrupts signals towards its interrupt controller parent
|
||||
|
||||
- controls how some of the interrupts will be flowing, whether they will
|
||||
directly output an interrupt signal towards the interrupt controller parent,
|
||||
or if they will output an interrupt signal at this 2nd level interrupt
|
||||
controller, in particular for UARTs
|
||||
|
||||
- not all 32-bits within the interrupt controller actually map to an interrupt
|
||||
|
||||
The typical hardware layout for this controller is represented below:
|
||||
|
||||
2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
|
||||
|
||||
0 -----[ MUX ] ------------|==========> GIC interrupt 75
|
||||
\-----------\
|
||||
|
|
||||
1 -----[ MUX ] --------)---|==========> GIC interrupt 76
|
||||
\------------|
|
||||
|
|
||||
2 -----[ MUX ] --------)---|==========> GIC interrupt 77
|
||||
\------------|
|
||||
|
|
||||
3 ---------------------|
|
||||
4 ---------------------|
|
||||
5 ---------------------|
|
||||
7 ---------------------|---|===========> GIC interrupt 66
|
||||
9 ---------------------|
|
||||
10 --------------------|
|
||||
11 --------------------/
|
||||
|
||||
6 ------------------------\
|
||||
|===========> GIC interrupt 64
|
||||
8 ------------------------/
|
||||
|
||||
12 ........................ X
|
||||
13 ........................ X (not connected)
|
||||
..
|
||||
31 ........................ X
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7120-l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
|
||||
node, valid values depend on the type of parent interrupt controller
|
||||
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
|
||||
are wired to this 2nd level interrupt controller, and how they match their
|
||||
respective interrupt parents. Should match exactly the number of interrupts
|
||||
specified in the 'interrupts' property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
|
||||
interrupts which have a mux gate, typically UARTs. Setting these bits will
|
||||
make their respective interrupts outputs bypass this 2nd level interrupt
|
||||
controller completely, it completely transparent for the interrupt controller
|
||||
parent
|
||||
|
||||
Example:
|
||||
|
||||
irq0_intc: interrupt-controller@f0406800 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
interrupt-parent = <&intc>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xf0406800 0x8>;
|
||||
interrupt-controller;
|
||||
interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
|
||||
brcm,int-map-mask = <0xeb8>, <0x140>;
|
||||
brcm,int-fwd-mask = <0x7>;
|
||||
};
|
|
@ -2,7 +2,13 @@ DT bindings for the R-/SH-Mobile irqpin controller
|
|||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "renesas,intc-irqpin"
|
||||
- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
|
||||
as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
|
||||
- "renesas,intc-irqpin-r8a7778" (R-Car M1A)
|
||||
- "renesas,intc-irqpin-r8a7779" (R-Car H1)
|
||||
- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
|
||||
|
|
|
@ -0,0 +1,32 @@
|
|||
DT bindings for the R-Mobile/R-Car interrupt controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,irqc-r8a73a4" (R-Mobile AP6)
|
||||
- "renesas,irqc-r8a7790" (R-Car H2)
|
||||
- "renesas,irqc-r8a7791" (R-Car M2-W)
|
||||
- "renesas,irqc-r8a7792" (R-Car V2H)
|
||||
- "renesas,irqc-r8a7793" (R-Car M2-N)
|
||||
- "renesas,irqc-r8a7794" (R-Car E2)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
|
||||
Optional properties:
|
||||
|
||||
- any properties, listed in interrupts.txt, and any standard resource allocation
|
||||
properties
|
||||
|
||||
Example:
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7790", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
|
@ -0,0 +1,36 @@
|
|||
Keystone 2 IRQ controller IP
|
||||
|
||||
On Keystone SOCs, DSP cores can send interrupts to ARM
|
||||
host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
|
||||
The IRQ handler running on HOST OS can identify DSP signal source by
|
||||
analyzing SRCCx bits in IPCARx registers. This is one of the component
|
||||
used by the IPC mechanism used on Keystone SOCs.
|
||||
|
||||
Required Properties:
|
||||
- compatible: should be "ti,keystone-irq"
|
||||
- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
|
||||
access device control registers and the offset inside
|
||||
device control registers range.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
|
||||
source should be 1.
|
||||
- interrupts: interrupt reference to primary interrupt controller
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
Example:
|
||||
kirq0: keystone_irq0@026202a0 {
|
||||
compatible = "ti,keystone-irq";
|
||||
ti,syscon-dev = <&devctrl 0x2a0>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
dsp0: dsp0 {
|
||||
compatible = "linux,rproc-user";
|
||||
...
|
||||
interrupt-parent = <&kirq0>;
|
||||
interrupts = <10 2>;
|
||||
};
|
|
@ -14,6 +14,7 @@ conditions.
|
|||
"arm,smmu-v1"
|
||||
"arm,smmu-v2"
|
||||
"arm,mmu-400"
|
||||
"arm,mmu-401"
|
||||
"arm,mmu-500"
|
||||
|
||||
depending on the particular implementation and/or the
|
||||
|
|
25
Documentation/devicetree/bindings/media/hix5hd2-ir.txt
Normal file
25
Documentation/devicetree/bindings/media/hix5hd2-ir.txt
Normal file
|
@ -0,0 +1,25 @@
|
|||
Device-Tree bindings for hix5hd2 ir IP
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "hisilicon,hix5hd2-ir".
|
||||
- reg: Base physical address of the controller and length of memory
|
||||
mapped region.
|
||||
- interrupts: interrupt-specifier for the sole interrupt generated by
|
||||
the device. The interrupt specifier format depends on the interrupt
|
||||
controller parent.
|
||||
- clocks: clock phandle and specifier pair.
|
||||
- hisilicon,power-syscon: phandle of syscon used to control power.
|
||||
|
||||
Optional properties:
|
||||
- linux,rc-map-name : Remote control map name.
|
||||
|
||||
Example node:
|
||||
|
||||
ir: ir@f8001000 {
|
||||
compatible = "hisilicon,hix5hd2-ir";
|
||||
reg = <0xf8001000 0x1000>;
|
||||
interrupts = <0 47 4>;
|
||||
clocks = <&clock HIX5HD2_FIXED_24M>;
|
||||
hisilicon,power-syscon = <&sysctrl>;
|
||||
linux,rc-map-name = "rc-tivo";
|
||||
};
|
|
@ -42,6 +42,13 @@ Optional properties:
|
|||
the chip default will be used. If present exactly five values must
|
||||
be specified.
|
||||
|
||||
- wlf,inmode : A list of INn_MODE register values, where n is the number
|
||||
of input signals. Valid values are 0 (Differential), 1 (Single-ended) and
|
||||
2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default.
|
||||
If present, values must be specified less than or equal to the number of
|
||||
input singals. If values less than the number of input signals, elements
|
||||
that has not been specifed are set to 0 by default.
|
||||
|
||||
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
|
||||
they are being externally supplied. As covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
|
15
Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
Normal file
15
Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
Normal file
|
@ -0,0 +1,15 @@
|
|||
* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)
|
||||
|
||||
The GPBR are a set of battery-backed registers.
|
||||
|
||||
Required properties:
|
||||
- compatible: "atmel,at91sam9260-gpbr", "syscon"
|
||||
- reg: contains offset/length value of the GPBR memory
|
||||
region.
|
||||
|
||||
Example:
|
||||
|
||||
gpbr: gpbr@fffffd50 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd50 0x10>;
|
||||
};
|
38
Documentation/devicetree/bindings/mfd/hi6421.txt
Normal file
38
Documentation/devicetree/bindings/mfd/hi6421.txt
Normal file
|
@ -0,0 +1,38 @@
|
|||
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
|
||||
|
||||
Required parent device properties:
|
||||
- compatible : contains "hisilicon,hi6421-pmic";
|
||||
- reg : register range space of hi6421;
|
||||
|
||||
Supported Hi6421 sub-devices include:
|
||||
|
||||
Device IRQ Names Supply Names Description
|
||||
------ --------- ------------ -----------
|
||||
regulators : None : None : Regulators
|
||||
|
||||
Required child device properties:
|
||||
None.
|
||||
|
||||
Example:
|
||||
hi6421 {
|
||||
compatible = "hisilicon,hi6421-pmic";
|
||||
reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */
|
||||
|
||||
regulators {
|
||||
// supply for MLC NAND/ eMMC
|
||||
hi6421_vout0_reg: hi6421_vout0 {
|
||||
regulator-name = "VOUT0";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
// supply for 26M Oscillator
|
||||
hi6421_vout1_reg: hi6421_vout1 {
|
||||
regulator-name = "VOUT1";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
146
Documentation/devicetree/bindings/mfd/max14577.txt
Normal file
146
Documentation/devicetree/bindings/mfd/max14577.txt
Normal file
|
@ -0,0 +1,146 @@
|
|||
Maxim MAX14577/77836 Multi-Function Device
|
||||
|
||||
MAX14577 is a Multi-Function Device with Micro-USB Interface Circuit, Li+
|
||||
Battery Charger and SFOUT LDO output for powering USB devices. It is
|
||||
interfaced to host controller using I2C.
|
||||
|
||||
MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "maxim,max14577" or "maxim,max77836".
|
||||
- reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836)
|
||||
- interrupts : IRQ line for the chip.
|
||||
- interrupt-parent : The parent interrupt controller.
|
||||
|
||||
|
||||
Required nodes:
|
||||
- charger :
|
||||
Node for configuring the charger driver.
|
||||
Required properties:
|
||||
- compatible : "maxim,max14577-charger"
|
||||
or "maxim,max77836-charger"
|
||||
- maxim,fast-charge-uamp : Current in uA for Fast Charge;
|
||||
Valid values:
|
||||
- for max14577: 90000 - 950000;
|
||||
- for max77836: 45000 - 475000;
|
||||
- maxim,eoc-uamp : Current in uA for End-Of-Charge mode;
|
||||
Valid values:
|
||||
- for max14577: 50000 - 200000;
|
||||
- for max77836: 5000 - 100000;
|
||||
- maxim,ovp-uvolt : OverVoltage Protection Threshold in uV;
|
||||
In an overvoltage condition, INT asserts and charging
|
||||
stops. Valid values:
|
||||
- 6000000, 6500000, 7000000, 7500000;
|
||||
- maxim,constant-uvolt : Battery Constant Voltage in uV;
|
||||
Valid values:
|
||||
- 4000000 - 4280000 (step by 20000);
|
||||
- 4350000;
|
||||
|
||||
|
||||
Optional nodes:
|
||||
- max14577-muic/max77836-muic :
|
||||
Node used only by extcon consumers.
|
||||
Required properties:
|
||||
- compatible : "maxim,max14577-muic" or "maxim,max77836-muic"
|
||||
|
||||
- regulators :
|
||||
Required properties:
|
||||
- compatible : "maxim,max14577-regulator"
|
||||
or "maxim,max77836-regulator"
|
||||
|
||||
May contain a sub-node per regulator from the list below. Each
|
||||
sub-node should contain the constraints and initialization information
|
||||
for that regulator. See regulator.txt for a description of standard
|
||||
properties for these sub-nodes.
|
||||
|
||||
List of valid regulator names:
|
||||
- for max14577: CHARGER, SAFEOUT.
|
||||
- for max77836: CHARGER, SAFEOUT, LDO1, LDO2.
|
||||
|
||||
The SAFEOUT is a fixed voltage regulator so there is no need to specify
|
||||
voltages for it.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
max14577@25 {
|
||||
compatible = "maxim,max14577";
|
||||
reg = <0x25>;
|
||||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 IRQ_TYPE_NONE>;
|
||||
|
||||
muic: max14577-muic {
|
||||
compatible = "maxim,max14577-muic";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "maxim,max14577-regulator";
|
||||
|
||||
SAFEOUT {
|
||||
regulator-name = "SAFEOUT";
|
||||
};
|
||||
CHARGER {
|
||||
regulator-name = "CHARGER";
|
||||
regulator-min-microamp = <90000>;
|
||||
regulator-max-microamp = <950000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
charger {
|
||||
compatible = "maxim,max14577-charger";
|
||||
|
||||
maxim,constant-uvolt = <4350000>;
|
||||
maxim,fast-charge-uamp = <450000>;
|
||||
maxim,eoc-uamp = <50000>;
|
||||
maxim,ovp-uvolt = <6500000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
max77836@25 {
|
||||
compatible = "maxim,max77836";
|
||||
reg = <0x25>;
|
||||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 IRQ_TYPE_NONE>;
|
||||
|
||||
muic: max77836-muic {
|
||||
compatible = "maxim,max77836-muic";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "maxim,max77836-regulator";
|
||||
|
||||
SAFEOUT {
|
||||
regulator-name = "SAFEOUT";
|
||||
};
|
||||
CHARGER {
|
||||
regulator-name = "CHARGER";
|
||||
regulator-min-microamp = <90000>;
|
||||
regulator-max-microamp = <950000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3950000>;
|
||||
};
|
||||
};
|
||||
|
||||
charger {
|
||||
compatible = "maxim,max77836-charger";
|
||||
|
||||
maxim,constant-uvolt = <4350000>;
|
||||
maxim,fast-charge-uamp = <225000>;
|
||||
maxim,eoc-uamp = <7500>;
|
||||
maxim,ovp-uvolt = <6500000>;
|
||||
};
|
||||
};
|
64
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
Normal file
64
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
Normal file
|
@ -0,0 +1,64 @@
|
|||
Qualcomm SPMI PMICs multi-function device bindings
|
||||
|
||||
The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
|
||||
PMICs. These PMICs use a QPNP scheme through SPMI interface.
|
||||
QPNP is effectively a partitioning scheme for dividing the SPMI extended
|
||||
register space up into logical pieces, and set of fixed register
|
||||
locations/definitions within these regions, with some of these regions
|
||||
specifically used for interrupt handling.
|
||||
|
||||
The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
|
||||
interfaced to the chip via the SPMI (System Power Management Interface) bus.
|
||||
Support for multiple independent functions are implemented by splitting the
|
||||
16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
|
||||
each. A function can consume one or more of these fixed-size register regions.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain one of:
|
||||
"qcom,pm8941"
|
||||
"qcom,pm8841"
|
||||
"qcom,pma8084"
|
||||
or generalized "qcom,spmi-pmic".
|
||||
- reg: Specifies the SPMI USID slave address for this device.
|
||||
For more information see:
|
||||
Documentation/devicetree/bindings/spmi/spmi.txt
|
||||
|
||||
Required properties for peripheral child nodes:
|
||||
- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
|
||||
|
||||
Optional properties for peripheral child nodes:
|
||||
- interrupts: Interrupts are specified as a 4-tuple. For more information
|
||||
see:
|
||||
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
|
||||
- interrupt-names: Corresponding interrupt name to the interrupts property
|
||||
|
||||
Each child node of SPMI slave id represents a function of the PMIC. In the
|
||||
example below the rtc device node represents a peripheral of pm8941
|
||||
SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
|
||||
|
||||
Example:
|
||||
|
||||
spmi {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
|
||||
pm8941@0 {
|
||||
compatible = "qcom,pm8941", "qcom,spmi-pmic";
|
||||
reg = <0x0 SPMI_USID>;
|
||||
|
||||
rtc {
|
||||
compatible = "qcom,rtc";
|
||||
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "alarm";
|
||||
};
|
||||
};
|
||||
|
||||
pm8941@1 {
|
||||
compatible = "qcom,pm8941", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
|
||||
regulator {
|
||||
compatible = "qcom,regulator";
|
||||
regulator-name = "8941_boost";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -61,6 +61,7 @@ The below bindings specify the set of valid subnodes.
|
|||
Definition: must be one of:
|
||||
"qcom,pm8058-rtc"
|
||||
"qcom,pm8921-rtc"
|
||||
"qcom,pm8941-rtc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
177
Documentation/devicetree/bindings/mfd/rk808.txt
Normal file
177
Documentation/devicetree/bindings/mfd/rk808.txt
Normal file
|
@ -0,0 +1,177 @@
|
|||
RK808 Power Management Integrated Circuit
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk808"
|
||||
- reg: I2C slave address
|
||||
- interrupt-parent: The parent interrupt controller.
|
||||
- interrupts: the interrupt outputs of the controller.
|
||||
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock binding to override the
|
||||
default output clock name
|
||||
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
|
||||
the system power.
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||
- vcc7-supply: The input supply for LDO_REG3 and LDO_REG7
|
||||
- vcc8-supply: The input supply for SWITCH_REG1
|
||||
- vcc9-supply: The input supply for LDO_REG4 and LDO_REG5
|
||||
- vcc10-supply: The input supply for LDO_REG6
|
||||
- vcc11-supply: The input supply for LDO_REG8
|
||||
- vcc12-supply: The input supply for SWITCH_REG2
|
||||
|
||||
Regulators: All the regulators of RK808 to be instantiated shall be
|
||||
listed in a child node named 'regulators'. Each regulator is represented
|
||||
by a child node of the 'regulators' node.
|
||||
|
||||
regulator-name {
|
||||
/* standard regulator bindings here */
|
||||
};
|
||||
|
||||
Following regulators of the RK808 PMIC block are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK808 datasheet.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 4.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 8.
|
||||
- SWITCH_REGn
|
||||
- valid values for n are 1 to 2
|
||||
|
||||
Standard regulator bindings are used inside regulator subnodes. Check
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
for more details
|
||||
|
||||
Example:
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
reg = <0x1b>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
|
||||
vcc8-supply = <&vcc_18>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc_io>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vccio_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-name = "vdd_arm";
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_io";
|
||||
};
|
||||
|
||||
vccio_pmu: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_pmu";
|
||||
};
|
||||
|
||||
vcc_tp: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_tp";
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
};
|
||||
|
||||
vcca_codec: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcca_codec";
|
||||
};
|
||||
|
||||
vcc_wl: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_wl";
|
||||
};
|
||||
|
||||
vcc_lcd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_lcd";
|
||||
};
|
||||
};
|
||||
};
|
36
Documentation/devicetree/bindings/mfd/rn5t618.txt
Normal file
36
Documentation/devicetree/bindings/mfd/rn5t618.txt
Normal file
|
@ -0,0 +1,36 @@
|
|||
* Ricoh RN5T618 PMIC
|
||||
|
||||
Ricoh RN5T618 is a power management IC which integrates 3 step-down
|
||||
DCDC converters, 7 low-dropout regulators, a Li-ion battery charger,
|
||||
fuel gauge, ADC, GPIOs and a watchdog timer. It can be controlled
|
||||
through a I2C interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ricoh,rn5t618"
|
||||
- reg: the I2C slave address of the device
|
||||
|
||||
Sub-nodes:
|
||||
- regulators: the node is required if the regulator functionality is
|
||||
needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, LDO1,
|
||||
LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
|
||||
The common bindings for each individual regulator can be found in:
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Example:
|
||||
|
||||
pmic@32 {
|
||||
compatible = "ricoh,rn5t618";
|
||||
reg = <0x32>;
|
||||
|
||||
regulators {
|
||||
DCDC1 {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
DCDC2 {
|
||||
regulator-min-microvolt = <1175000>;
|
||||
regulator-max-microvolt = <1175000>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -13,6 +13,7 @@ Optional properties:
|
|||
- interrupt-parent : Specifies which IRQ controller we're connected to
|
||||
- wakeup-source : Marks the input device as wakable
|
||||
- st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
|
||||
- irq-gpio : If present, which GPIO to use for event IRQ
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -23,8 +23,13 @@ down during off-idle. Note that this does not work on all boards
|
|||
depending on how the external oscillator is wired.
|
||||
|
||||
Optional properties:
|
||||
- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
|
||||
SLEEP-to-OFF transition when the system poweroffs.
|
||||
|
||||
- ti,system-power-controller: This indicates that TWL4030 is the
|
||||
power supply master of the system. With this flag, the chip will
|
||||
initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the
|
||||
system poweroffs.
|
||||
|
||||
- ti,use_poweroff: Deprecated name for ti,system-power-controller
|
||||
|
||||
Example:
|
||||
&i2c1 {
|
||||
|
|
|
@ -40,6 +40,8 @@ Optional properties:
|
|||
- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
|
||||
- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
|
||||
- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
|
||||
- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
|
||||
programmed with. Valid range: [0 .. 0xffff].
|
||||
|
||||
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
|
||||
polarity properties, we have to fix the meaning of the "normal" and "inverted"
|
||||
|
|
|
@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
|
|||
Required Properties:
|
||||
|
||||
* compatible: should be
|
||||
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following
|
||||
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
|
||||
before RK3288
|
||||
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
|
||||
|
||||
Example:
|
||||
|
||||
rkdwmmc0@12200000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x12200000 0x1000>;
|
||||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -19,6 +19,9 @@ Required properties:
|
|||
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
|
||||
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
|
||||
"renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
|
||||
"renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
|
||||
"renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
|
||||
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
|
||||
|
||||
Optional properties:
|
||||
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
|
||||
|
|
|
@ -36,6 +36,7 @@ Optional properties:
|
|||
- reg : should specify the address and size used for NFC command registers,
|
||||
NFC registers and NFC Sram. NFC Sram address and size can be absent
|
||||
if don't want to use it.
|
||||
- clocks: phandle to the peripheral clock
|
||||
- Optional properties:
|
||||
- atmel,write-by-sram: boolean to enable NFC write by sram.
|
||||
|
||||
|
@ -98,6 +99,7 @@ nand0: nand@40000000 {
|
|||
compatible = "atmel,sama5d3-nfc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&hsmc_clk>
|
||||
reg = <
|
||||
0x70000000 0x10000000 /* NFC Command Registers */
|
||||
0xffffc000 0x00000070 /* NFC HSMC regs */
|
||||
|
|
|
@ -4,8 +4,8 @@ Flash chips (Memory Technology Devices) are often used for solid state
|
|||
file systems on embedded devices.
|
||||
|
||||
- compatible : should contain the specific model of mtd chip(s)
|
||||
used, if known, followed by either "cfi-flash", "jedec-flash"
|
||||
or "mtd-ram".
|
||||
used, if known, followed by either "cfi-flash", "jedec-flash",
|
||||
"mtd-ram" or "mtd-rom".
|
||||
- reg : Address range(s) of the mtd chip(s)
|
||||
It's possible to (optionally) define multiple "reg" tuples so that
|
||||
non-identical chips can be described in one node.
|
||||
|
|
|
@ -3,7 +3,7 @@ APM X-Gene SoC Ethernet nodes
|
|||
Ethernet nodes are defined to describe on-chip ethernet interfaces in
|
||||
APM X-Gene SoC.
|
||||
|
||||
Required properties:
|
||||
Required properties for all the ethernet interfaces:
|
||||
- compatible: Should be "apm,xgene-enet"
|
||||
- reg: Address and length of the register set for the device. It contains the
|
||||
information of registers in the same order as described by reg-names
|
||||
|
@ -15,6 +15,8 @@ Required properties:
|
|||
- clocks: Reference to the clock entry.
|
||||
- local-mac-address: MAC address assigned to this device
|
||||
- phy-connection-type: Interface type between ethernet device and PHY device
|
||||
|
||||
Required properties for ethernet interfaces that have external PHY:
|
||||
- phy-handle: Reference to a PHY node connected to this device
|
||||
|
||||
- mdio: Device tree subnode with the following required properties:
|
||||
|
|
|
@ -16,3 +16,9 @@ Optional properties:
|
|||
KSZ8051: register 0x1f, bits 5..4
|
||||
|
||||
See the respective PHY datasheet for the mode values.
|
||||
|
||||
- clocks, clock-names: contains clocks according to the common clock bindings.
|
||||
|
||||
supported clocks:
|
||||
- KSZ8021, KSZ8031: "rmii-ref": The RMII refence input clock. Used
|
||||
to determine the XI input clock.
|
||||
|
|
|
@ -1,58 +1,65 @@
|
|||
STMicroelectronics SoC DWMAC glue layer controller
|
||||
|
||||
This file documents differences between the core properties in
|
||||
Documentation/devicetree/bindings/net/stmmac.txt
|
||||
and what is needed on STi platforms to program the stmmac glue logic.
|
||||
|
||||
The device node has following properties.
|
||||
|
||||
Required properties:
|
||||
- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
|
||||
"st,stid127-dwmac".
|
||||
- reg : Offset of the glue configuration register map in system
|
||||
- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
|
||||
"st,stih407-dwmac", "st,stid127-dwmac".
|
||||
- reg : Offset of the glue configuration register map in system
|
||||
configuration regmap pointed by st,syscon property and size.
|
||||
|
||||
- reg-names : Should be "sti-ethconf".
|
||||
|
||||
- st,syscon : Should be phandle to system configuration node which
|
||||
- st,syscon : Should be phandle to system configuration node which
|
||||
encompases this glue registers.
|
||||
- st,gmac_en: this is to enable the gmac into a dedicated sysctl control
|
||||
register available on STiH407 SoC.
|
||||
- sti-ethconf: this is the gmac glue logic register to enable the GMAC,
|
||||
select among the different modes and program the clk retiming.
|
||||
- pinctrl-0: pin-control for all the MII mode supported.
|
||||
|
||||
- st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
|
||||
wired up in from different sources. One via TXCLK pin and other via CLK_125
|
||||
pin. This wiring is totally board dependent. However the retiming glue
|
||||
logic should be configured accordingly. Possible values for this property
|
||||
|
||||
"txclk" - if 125Mhz clock is wired up via txclk line.
|
||||
"clk_125" - if 125Mhz clock is wired up via clk_125 line.
|
||||
|
||||
This property is only valid for Giga bit setup( GMII, RGMII), and it is
|
||||
un-used for non-giga bit (MII and RMII) setups. Also note that internal
|
||||
clockgen can not generate stable 125Mhz clock.
|
||||
|
||||
- st,ext-phyclk: This boolean property indicates who is generating the clock
|
||||
for tx and rx. This property is only valid for RMII case where the clock can
|
||||
be generated from the MAC or PHY.
|
||||
|
||||
- clock-names: should be "sti-ethclk".
|
||||
- clocks: Should point to ethernet clockgen which can generate phyclk.
|
||||
|
||||
Optional properties:
|
||||
- resets : phandle pointing to the system reset controller with correct
|
||||
reset line index for ethernet reset.
|
||||
- st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
|
||||
MAC can generate it.
|
||||
- st,tx-retime-src: This specifies which clk is wired up to the mac for
|
||||
retimeing tx lines. This is totally board dependent and can take one of the
|
||||
posssible values from "txclk", "clk_125" or "clkgen".
|
||||
If not passed, the internal clock will be used by default.
|
||||
- sti-ethclk: this is the phy clock.
|
||||
- sti-clkconf: this is an extra sysconfig register, available in new SoCs,
|
||||
to program the clk retiming.
|
||||
- st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
|
||||
STiH407.
|
||||
|
||||
Example:
|
||||
|
||||
ethernet0: dwmac@fe810000 {
|
||||
device_type = "network";
|
||||
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
||||
reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
phy-mode = "mii";
|
||||
ethernet0: dwmac@9630000 {
|
||||
device_type = "network";
|
||||
status = "disabled";
|
||||
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
||||
reg = <0x9630000 0x8000>, <0x80 0x4>;
|
||||
reg-names = "stmmaceth", "sti-ethconf";
|
||||
|
||||
st,syscon = <&syscfg_rear>;
|
||||
st,syscon = <&syscfg_sbc_reg>;
|
||||
st,gmac_en;
|
||||
resets = <&softreset STIH407_ETH1_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
|
||||
snps,pbl = <32>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 99 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 100 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
|
||||
|
||||
snps,pbl = <32>;
|
||||
snps,mixed-burst;
|
||||
|
||||
resets = <&softreset STIH416_ETH0_SOFTRESET>;
|
||||
reset-names = "stmmaceth";
|
||||
pinctrl-0 = <&pinctrl_mii0>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&CLK_S_GMAC0_PHY>;
|
||||
clock-names = "stmmaceth";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgmii1>;
|
||||
|
||||
clock-names = "stmmaceth", "sti-ethclk";
|
||||
clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
|
||||
<&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
AU Optronics Corporation 10.1" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "auo,b101xtn01"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -23,3 +23,6 @@ Required properties:
|
|||
|
||||
Optional properties:
|
||||
- reset-gpio: gpio pin number of power good signal
|
||||
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
|
||||
specify this property, to keep backwards compatibility a range of 0x00-0xff
|
||||
is assumed if not present)
|
||||
|
|
27
Documentation/devicetree/bindings/pci/fsl,pci.txt
Normal file
27
Documentation/devicetree/bindings/pci/fsl,pci.txt
Normal file
|
@ -0,0 +1,27 @@
|
|||
* Bus Enumeration by Freescale PCI-X Agent
|
||||
|
||||
Typically any Freescale PCI-X bridge hardware strapped into Agent mode
|
||||
is prevented from enumerating the bus. The PrPMC form-factor requires
|
||||
all mezzanines to be PCI-X Agents, but one per system may still
|
||||
enumerate the bus.
|
||||
|
||||
The property defined below will allow a PCI-X bridge to be used for bus
|
||||
enumeration despite being strapped into Agent mode.
|
||||
|
||||
Required properties:
|
||||
- fsl,pci-agent-force-enum : There is no value associated with this
|
||||
property. The property itself is treated as a boolean.
|
||||
|
||||
Example:
|
||||
|
||||
/* PCI-X bridge known to be PrPMC Monarch */
|
||||
pci0: pci@ef008000 {
|
||||
fsl,pci-agent-force-enum;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
...
|
||||
...
|
||||
};
|
|
@ -1,7 +1,10 @@
|
|||
NVIDIA Tegra PCIe controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
|
||||
- compatible: Must be one of:
|
||||
- "nvidia,tegra20-pcie"
|
||||
- "nvidia,tegra30-pcie"
|
||||
- "nvidia,tegra124-pcie"
|
||||
- device_type: Must be "pci"
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names property.
|
||||
|
@ -57,6 +60,11 @@ Required properties:
|
|||
- afi
|
||||
- pcie_x
|
||||
|
||||
Required properties on Tegra124 and later:
|
||||
- phys: Must contain an entry for each entry in phy-names.
|
||||
- phy-names: Must include the following entries:
|
||||
- pcie
|
||||
|
||||
Power supplies for Tegra20:
|
||||
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
|
@ -84,6 +92,21 @@ Power supplies for Tegra30:
|
|||
- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
|
||||
Power supplies for Tegra124:
|
||||
- Required:
|
||||
- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
|
||||
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
|
||||
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
|
||||
supply 1.05 V.
|
||||
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
|
||||
Must supply 3.3 V.
|
||||
- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
|
||||
Must supply 3.3 V.
|
||||
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
|
||||
supply 2.8-3.3 V.
|
||||
- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
|
||||
supply 1.05 V.
|
||||
|
||||
Root ports are defined as subnodes of the PCIe controller node.
|
||||
|
||||
Required properties:
|
||||
|
|
63
Documentation/devicetree/bindings/pci/pci-keystone.txt
Normal file
63
Documentation/devicetree/bindings/pci/pci-keystone.txt
Normal file
|
@ -0,0 +1,63 @@
|
|||
TI Keystone PCIe interface
|
||||
|
||||
Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
|
||||
It shares common functions with PCIe Designware core driver and inherit
|
||||
common properties defined in
|
||||
Documentation/devicetree/bindings/pci/designware-pci.txt
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
|
||||
for the details of Designware DT bindings. Additional properties are
|
||||
described here as well as properties that are not applicable.
|
||||
|
||||
Required Properties:-
|
||||
|
||||
compatibility: "ti,keystone-pcie"
|
||||
reg: index 1 is the base address and length of DW application registers.
|
||||
index 2 is the base address and length of PCI device ID register.
|
||||
|
||||
pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
|
||||
interrupt-cells: should be set to 1
|
||||
interrupt-parent: Parent interrupt controller phandle
|
||||
interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
|
||||
|
||||
Example:
|
||||
pcie_msi_intc: msi-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie_intc: Interrupt controller device node for Legacy IRQ chip
|
||||
interrupt-cells: should be set to 1
|
||||
interrupt-parent: Parent interrupt controller phandle
|
||||
interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
|
||||
|
||||
Example:
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
Optional properties:-
|
||||
phys: phandle to Generic Keystone SerDes phy for PCI
|
||||
phy-names: name of the Generic Keystine SerDes phy for PCI
|
||||
- If boot loader already does PCI link establishment, then phys and
|
||||
phy-names shouldn't be present.
|
||||
|
||||
Designware DT Properties not applicable for Keystone PCI
|
||||
|
||||
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
|
||||
|
57
Documentation/devicetree/bindings/pci/xgene-pci.txt
Normal file
57
Documentation/devicetree/bindings/pci/xgene-pci.txt
Normal file
|
@ -0,0 +1,57 @@
|
|||
* AppliedMicro X-Gene PCIe interface
|
||||
|
||||
Required properties:
|
||||
- device_type: set to "pci"
|
||||
- compatible: should contain "apm,xgene-pcie" to identify the core.
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names
|
||||
property.
|
||||
- reg-names: Must include the following entries:
|
||||
"csr": controller configuration registers.
|
||||
"cfg": pcie configuration space registers.
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
- ranges: ranges for the outbound memory, I/O regions.
|
||||
- dma-ranges: ranges for the inbound memory regions.
|
||||
- #interrupt-cells: set to <1>
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
||||
to define the mapping of the PCIe interface to interrupt
|
||||
numbers.
|
||||
- clocks: from common clock binding: handle to pci clock.
|
||||
|
||||
Optional properties:
|
||||
- status: Either "ok" or "disabled".
|
||||
- dma-coherent: Present if dma operations are coherent
|
||||
|
||||
Example:
|
||||
|
||||
SoC specific DT Entry:
|
||||
|
||||
pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
};
|
||||
|
||||
|
||||
Board specific DT Entry:
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
62
Documentation/devicetree/bindings/pci/xilinx-pcie.txt
Normal file
62
Documentation/devicetree/bindings/pci/xilinx-pcie.txt
Normal file
|
@ -0,0 +1,62 @@
|
|||
* Xilinx AXI PCIe Root Port Bridge DT description
|
||||
|
||||
Required properties:
|
||||
- #address-cells: Address representation for root ports, set to <3>
|
||||
- #size-cells: Size representation for root ports, set to <2>
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
|
||||
- reg: Should contain AXI PCIe registers location and length
|
||||
- device_type: must be "pci"
|
||||
- interrupts: Should contain AXI PCIe interrupt
|
||||
- interrupt-map-mask,
|
||||
interrupt-map: standard PCI properties to define the mapping of the
|
||||
PCI interface to interrupt numbers.
|
||||
- ranges: ranges for the PCI memory regions (I/O space region is not
|
||||
supported by hardware)
|
||||
Please refer to the standard PCI bus binding document for a more
|
||||
detailed explanation
|
||||
|
||||
Optional properties:
|
||||
- bus-range: PCI bus numbers covered
|
||||
|
||||
Interrupt controller child node
|
||||
+++++++++++++++++++++++++++++++
|
||||
Required properties:
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #address-cells: specifies the number of cells needed to encode an
|
||||
address. The value must be 0.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 1.
|
||||
|
||||
NOTE:
|
||||
The core provides a single interrupt for both INTx/MSI messages. So,
|
||||
created a interrupt controller node to support 'interrupt-map' DT
|
||||
functionality. The driver will create an IRQ domain for this map, decode
|
||||
the four INTx interrupts in ISR and route them to this domain.
|
||||
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
pci_express: axi-pcie@50000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "xlnx,axi-pcie-host-1.00.a";
|
||||
reg = < 0x50000000 0x10000000 >;
|
||||
device_type = "pci";
|
||||
interrupts = < 0 52 4 >;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 1>,
|
||||
<0 0 0 2 &pcie_intc 2>,
|
||||
<0 0 0 3 &pcie_intc 3>,
|
||||
<0 0 0 4 &pcie_intc 4>;
|
||||
ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
}
|
||||
};
|
49
Documentation/devicetree/bindings/power/power_domain.txt
Normal file
49
Documentation/devicetree/bindings/power/power_domain.txt
Normal file
|
@ -0,0 +1,49 @@
|
|||
* Generic PM domains
|
||||
|
||||
System on chip designs are often divided into multiple PM domains that can be
|
||||
used for power gating of selected IP blocks for power saving by reduced leakage
|
||||
current.
|
||||
|
||||
This device tree binding can be used to bind PM domain consumer devices with
|
||||
their PM domains provided by PM domain providers. A PM domain provider can be
|
||||
represented by any node in the device tree and can provide one or more PM
|
||||
domains. A consumer node can refer to the provider by a phandle and a set of
|
||||
phandle arguments (so called PM domain specifiers) of length specified by the
|
||||
#power-domain-cells property in the PM domain provider node.
|
||||
|
||||
==PM domain providers==
|
||||
|
||||
Required properties:
|
||||
- #power-domain-cells : Number of cells in a PM domain specifier;
|
||||
Typically 0 for nodes representing a single PM domain and 1 for nodes
|
||||
providing multiple PM domains (e.g. power controllers), but can be any value
|
||||
as specified by device tree binding documentation of particular provider.
|
||||
|
||||
Example:
|
||||
|
||||
power: power-controller@12340000 {
|
||||
compatible = "foo,power-controller";
|
||||
reg = <0x12340000 0x1000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
The node above defines a power controller that is a PM domain provider and
|
||||
expects one cell as its phandle argument.
|
||||
|
||||
==PM domain consumers==
|
||||
|
||||
Required properties:
|
||||
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle.
|
||||
|
||||
Example:
|
||||
|
||||
leaky-device@12350000 {
|
||||
compatible = "foo,i-leak-current";
|
||||
reg = <0x12350000 0x1000>;
|
||||
power-domains = <&power 0>;
|
||||
};
|
||||
|
||||
The node above defines a typical PM domain consumer device, which is located
|
||||
inside a PM domain with index 0 of a power controller represented by a node
|
||||
with the label "power".
|
|
@ -0,0 +1,26 @@
|
|||
Binding for the LTC2952 PowerPath controller
|
||||
|
||||
This chip is used to externally trigger a system shut down. Once the trigger has
|
||||
been sent, the chips' watchdog has to be reset to gracefully shut down.
|
||||
If the Linux systems decides to shut down it powers off the platform via the
|
||||
kill signal.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must contain: "lltc,ltc2952"
|
||||
- trigger-gpios: phandle + gpio-specifier for the GPIO connected to the
|
||||
chip's trigger line
|
||||
- watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the
|
||||
chip's watchdog line
|
||||
- kill-gpios: phandle + gpio-specifier for the GPIO connected to the
|
||||
chip's kill line
|
||||
|
||||
Example:
|
||||
|
||||
ltc2952 {
|
||||
compatible = "lltc,ltc2952";
|
||||
|
||||
trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
|
||||
watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
11
Documentation/devicetree/bindings/power/reset/st-reset.txt
Normal file
11
Documentation/devicetree/bindings/power/reset/st-reset.txt
Normal file
|
@ -0,0 +1,11 @@
|
|||
*Device-Tree bindings for ST SW reset functionality
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "st,<chip>-restart".
|
||||
- st,syscfg: should be a phandle of the syscfg node.
|
||||
|
||||
Example node:
|
||||
restart {
|
||||
compatible = "st,stih416-restart";
|
||||
st,syscfg = <&syscfg_sbc>;
|
||||
};
|
|
@ -0,0 +1,23 @@
|
|||
Generic SYSCON mapped register reset driver
|
||||
|
||||
This is a generic reset driver using syscon to map the reset register.
|
||||
The reset is generally performed with a write to the reset register
|
||||
defined by the register map pointed by syscon reference plus the offset
|
||||
with the mask defined in the reboot node.
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain "syscon-reboot"
|
||||
- regmap: this is phandle to the register map node
|
||||
- offset: offset in the register map for the reboot register (in bytes)
|
||||
- mask: the reset value written to the reboot register (32 bit access)
|
||||
|
||||
Default will be little endian mode, 32 bit access only.
|
||||
|
||||
Examples:
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <®mapnode>;
|
||||
offset = <0x0>;
|
||||
mask = <0x1>;
|
||||
};
|
|
@ -0,0 +1,83 @@
|
|||
Rockchip SRAM for IO Voltage Domains:
|
||||
-------------------------------------
|
||||
|
||||
IO domain voltages on some Rockchip SoCs are variable but need to be
|
||||
kept in sync between the regulators and the SoC using a special
|
||||
register.
|
||||
|
||||
A specific example using rk3288:
|
||||
- If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
|
||||
bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to
|
||||
that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1.
|
||||
|
||||
Said another way, this driver simply handles keeping bits in the SoC's
|
||||
general register file (GRF) in sync with the actual value of a voltage
|
||||
hooked up to the pins.
|
||||
|
||||
Note that this driver specifically doesn't include:
|
||||
- any logic for deciding what voltage we should set regulators to
|
||||
- any logic for deciding whether regulators (or internal SoC blocks)
|
||||
should have power or not have power
|
||||
|
||||
If there were some other software that had the smarts of making
|
||||
decisions about regulators, it would work in conjunction with this
|
||||
driver. When that other software adjusted a regulator's voltage then
|
||||
this driver would handle telling the SoC about it. A good example is
|
||||
vqmmc for SD. In that case the dw_mmc driver simply is told about a
|
||||
regulator. It changes the regulator between 3.3V and 1.8V at the
|
||||
right time. This driver notices the change and makes sure that the
|
||||
SoC is on the same page.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of:
|
||||
- "rockchip,rk3188-io-voltage-domain" for rk3188
|
||||
- "rockchip,rk3288-io-voltage-domain" for rk3288
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
|
||||
|
||||
You specify supplies using the standard regulator bindings by including
|
||||
a phandle the the relevant regulator. All specified supplies must be able
|
||||
to report their voltage. The IO Voltage Domain for any non-specified
|
||||
supplies will be not be touched.
|
||||
|
||||
Possible supplies for rk3188:
|
||||
- ap0-supply: The supply connected to AP0_VCC.
|
||||
- ap1-supply: The supply connected to AP1_VCC.
|
||||
- cif-supply: The supply connected to CIF_VCC.
|
||||
- flash-supply: The supply connected to FLASH_VCC.
|
||||
- lcdc0-supply: The supply connected to LCD0_VCC.
|
||||
- lcdc1-supply: The supply connected to LCD1_VCC.
|
||||
- vccio0-supply: The supply connected to VCCIO0.
|
||||
- vccio1-supply: The supply connected to VCCIO1.
|
||||
Sometimes also labeled VCCIO1 and VCCIO2.
|
||||
|
||||
Possible supplies for rk3288:
|
||||
- audio-supply: The supply connected to APIO4_VDD.
|
||||
- bb-supply: The supply connected to APIO5_VDD.
|
||||
- dvp-supply: The supply connected to DVPIO_VDD.
|
||||
- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC
|
||||
- flash1-supply: The supply connected to FLASH1_VDD. Also known as SDIO1.
|
||||
- gpio30-supply: The supply connected to APIO1_VDD.
|
||||
- gpio1830 The supply connected to APIO2_VDD.
|
||||
- lcdc-supply: The supply connected to LCDC_VDD.
|
||||
- sdcard-supply: The supply connected to SDMMC0_VDD.
|
||||
- wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
io-domains {
|
||||
compatible = "rockchip,rk3288-io-voltage-domain";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
audio-supply = <&vcc18_codec>;
|
||||
bb-supply = <&vcc33_io>;
|
||||
dvp-supply = <&vcc_18>;
|
||||
flash0-supply = <&vcc18_flashio>;
|
||||
gpio1830-supply = <&vcc33_io>;
|
||||
gpio30-supply = <&vcc33_pmuio>;
|
||||
lcdc-supply = <&vcc33_lcd>;
|
||||
sdcard-supply = <&vccio_sd>;
|
||||
wifi-supply = <&vcc18_wl>;
|
||||
};
|
18
Documentation/devicetree/bindings/rtc/dallas,ds1339.txt
Normal file
18
Documentation/devicetree/bindings/rtc/dallas,ds1339.txt
Normal file
|
@ -0,0 +1,18 @@
|
|||
* Dallas DS1339 I2C Serial Real-Time Clock
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "dallas,ds1339".
|
||||
- reg: I2C address for chip
|
||||
|
||||
Optional properties:
|
||||
- trickle-resistor-ohms : Selected resistor for trickle charger
|
||||
Values usable for ds1339 are 250, 2000, 4000
|
||||
Should be given if trickle charger should be enabled
|
||||
- trickle-diode-disable : Do not use internal trickle charger diode
|
||||
Should be given if internal trickle charger diode should be disabled
|
||||
Example:
|
||||
ds1339: rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
trickle-resistor-ohms = <250>;
|
||||
reg = <0x68>;
|
||||
};
|
|
@ -3,7 +3,10 @@
|
|||
Required properties:
|
||||
- compatible: should be one of the following.
|
||||
* "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
|
||||
* "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc.
|
||||
* "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc.
|
||||
* "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
|
||||
* "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: Two interrupt numbers to the cpu should be specified. First
|
||||
|
|
19
Documentation/devicetree/bindings/sound/adi,ssm2602.txt
Normal file
19
Documentation/devicetree/bindings/sound/adi,ssm2602.txt
Normal file
|
@ -0,0 +1,19 @@
|
|||
Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices
|
||||
|
||||
SSM2602 support both I2C and SPI as the configuration interface,
|
||||
the selection is made by the MODE strap-in pin.
|
||||
SSM2603 and SSM2604 only support I2C as the configuration interface.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604"
|
||||
|
||||
- reg : the I2C address of the device for I2C, the chip select
|
||||
number for SPI.
|
||||
|
||||
Example:
|
||||
|
||||
ssm2602: ssm2602@1a {
|
||||
compatible = "adi,ssm2602";
|
||||
reg = <0x1a>;
|
||||
};
|
62
Documentation/devicetree/bindings/sound/cs35l32.txt
Normal file
62
Documentation/devicetree/bindings/sound/cs35l32.txt
Normal file
|
@ -0,0 +1,62 @@
|
|||
CS35L32 audio CODEC
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "cirrus,cs35l32"
|
||||
|
||||
- reg : the I2C address of the device for I2C. Address is determined by the level
|
||||
of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
|
||||
|
||||
- VA-supply, VP-supply : power supplies for the device,
|
||||
as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset-gpios : a GPIO spec for the reset pin. If specified, it will be
|
||||
deasserted before communication to the codec starts.
|
||||
|
||||
- cirrus,boost-manager : Boost voltage control.
|
||||
0 = Automatically managed. Boost-converter output voltage is the higher
|
||||
of the two: Class G or adaptive LED voltage.
|
||||
1 = Automatically managed irrespective of audio, adapting for low-power
|
||||
dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
|
||||
if LEDs are OFF (VBST = VP).
|
||||
2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP).
|
||||
3 = Boost voltage fixed at 5 V.
|
||||
|
||||
- cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only.
|
||||
Determines the data packed in a two-CS35L32 configuration.
|
||||
0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0].
|
||||
1 = Left/right channels VMON[11:0], IMON[11:0], STATUS.
|
||||
2 = (Default) left/right channels VMON[15:0], IMON [15:0].
|
||||
3 = Left/right channels VPMON[7:0], STATUS.
|
||||
|
||||
- cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32
|
||||
devices are on board sharing SDOUT.
|
||||
0 = (Default) One IC.
|
||||
1 = Two IC's.
|
||||
|
||||
- cirrus,battery-recovery : Low battery nominal recovery threshold, rising VP.
|
||||
0 = 3.1V
|
||||
1 = 3.2V
|
||||
2 = 3.3V (Default)
|
||||
3 = 3.4V
|
||||
|
||||
- cirrus,battery-threshold : Low battery nominal threshold, falling VP.
|
||||
0 = 3.1V
|
||||
1 = 3.2V
|
||||
2 = 3.3V
|
||||
3 = 3.4V (Default)
|
||||
4 = 3.5V
|
||||
5 = 3.6V
|
||||
|
||||
Example:
|
||||
|
||||
codec: codec@40 {
|
||||
compatible = "cirrus,cs35l32";
|
||||
reg = <0x40>;
|
||||
reset-gpios = <&gpio 10 0>;
|
||||
cirrus,boost-manager = <0x03>;
|
||||
cirrus,sdout-datacfg = <0x02>;
|
||||
VA-supply = <®_audio>;
|
||||
};
|
38
Documentation/devicetree/bindings/sound/es8328.txt
Normal file
38
Documentation/devicetree/bindings/sound/es8328.txt
Normal file
|
@ -0,0 +1,38 @@
|
|||
Everest ES8328 audio CODEC
|
||||
|
||||
This device supports both I2C and SPI.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "everest,es8328"
|
||||
- DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
|
||||
- AVDD-supply : Regulator providing analog supply voltage 3.3V
|
||||
- PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
|
||||
- IPVDD-supply : Regulator providing analog output voltage 3.3V
|
||||
- clocks : A 22.5792 or 11.2896 MHz clock
|
||||
- reg : the I2C address of the device for I2C, the chip select number for SPI
|
||||
|
||||
Pins on the device (for linking into audio routes):
|
||||
|
||||
* LOUT1
|
||||
* LOUT2
|
||||
* ROUT1
|
||||
* ROUT2
|
||||
* LINPUT1
|
||||
* RINPUT1
|
||||
* LINPUT2
|
||||
* RINPUT2
|
||||
* Mic Bias
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
codec: es8328@11 {
|
||||
compatible = "everest,es8328";
|
||||
DVDD-supply = <®_3p3v>;
|
||||
AVDD-supply = <®_3p3v>;
|
||||
PVDD-supply = <®_3p3v>;
|
||||
HPVDD-supply = <®_3p3v>;
|
||||
clocks = <&clks 169>;
|
||||
reg = <0x11>;
|
||||
};
|
|
@ -7,7 +7,8 @@ other DSPs. It has up to six transmitters and four receivers.
|
|||
|
||||
Required properties:
|
||||
|
||||
- compatible : Compatible list, must contain "fsl,imx35-esai".
|
||||
- compatible : Compatible list, must contain "fsl,imx35-esai" or
|
||||
"fsl,vf610-esai"
|
||||
|
||||
- reg : Offset and length of the register set for the device.
|
||||
|
||||
|
|
|
@ -58,13 +58,7 @@ Optional properties:
|
|||
Documentation/devicetree/bindings/dma/dma.txt.
|
||||
- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
|
||||
is not defined.
|
||||
- fsl,mode: The operating mode for the SSI interface.
|
||||
"i2s-slave" - I2S mode, SSI is clock slave
|
||||
"i2s-master" - I2S mode, SSI is clock master
|
||||
"lj-slave" - left-justified mode, SSI is clock slave
|
||||
"lj-master" - l.j. mode, SSI is clock master
|
||||
"rj-slave" - right-justified mode, SSI is clock slave
|
||||
"rj-master" - r.j., SSI is clock master
|
||||
- fsl,mode: The operating mode for the AC97 interface only.
|
||||
"ac97-slave" - AC97 mode, SSI is clock slave
|
||||
"ac97-master" - AC97 mode, SSI is clock master
|
||||
|
||||
|
|
82
Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
Normal file
82
Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
Normal file
|
@ -0,0 +1,82 @@
|
|||
Freescale Generic ASoC Sound Card with ASRC support
|
||||
|
||||
The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale
|
||||
SoCs connecting with external CODECs.
|
||||
|
||||
The idea of this generic sound card is a bit like ASoC Simple Card. However,
|
||||
for Freescale SoCs (especially those released in recent years), most of them
|
||||
have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And
|
||||
this is a specific feature that might be painstakingly controlled and merged
|
||||
into the Simple Card.
|
||||
|
||||
So having this generic sound card allows all Freescale SoC users to benefit
|
||||
from the simplification of a new card support and the capability of the wide
|
||||
sample rates support through ASRC.
|
||||
|
||||
Note: The card is initially designed for those sound cards who use I2S and
|
||||
PCM DAI formats. However, it'll be also possible to support those non
|
||||
I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long
|
||||
as the driver has been properly upgraded.
|
||||
|
||||
|
||||
The compatible list for this generic sound card currently:
|
||||
"fsl,imx-audio-cs42888"
|
||||
|
||||
"fsl,imx-audio-wm8962"
|
||||
(compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt)
|
||||
|
||||
"fsl,imx-audio-sgtl5000"
|
||||
(compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Contains one of entries in the compatible list.
|
||||
|
||||
- model : The user-visible name of this sound complex
|
||||
|
||||
- audio-cpu : The phandle of an CPU DAI controller
|
||||
|
||||
- audio-codec : The phandle of an audio codec
|
||||
|
||||
- audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the
|
||||
connection's sink, the second being the connection's
|
||||
source. There're a few pre-designed board connectors:
|
||||
* Line Out Jack
|
||||
* Line In Jack
|
||||
* Headphone Jack
|
||||
* Mic Jack
|
||||
* Ext Spk
|
||||
* AMIC (stands for Analog Microphone Jack)
|
||||
* DMIC (stands for Digital Microphone Jack)
|
||||
|
||||
Note: The "Mic Jack" and "AMIC" are redundant while
|
||||
coexsiting in order to support the old bindings
|
||||
of wm8962 and sgtl5000.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- audio-asrc : The phandle of ASRC. It can be absent if there's no
|
||||
need to add ASRC support via DPCM.
|
||||
|
||||
Example:
|
||||
sound-cs42888 {
|
||||
compatible = "fsl,imx-audio-cs42888";
|
||||
model = "cs42888-audio";
|
||||
audio-cpu = <&esai>;
|
||||
audio-asrc = <&asrc>;
|
||||
audio-codec = <&cs42888>;
|
||||
audio-routing =
|
||||
"Line Out Jack", "AOUT1L",
|
||||
"Line Out Jack", "AOUT1R",
|
||||
"Line Out Jack", "AOUT2L",
|
||||
"Line Out Jack", "AOUT2R",
|
||||
"Line Out Jack", "AOUT3L",
|
||||
"Line Out Jack", "AOUT3R",
|
||||
"Line Out Jack", "AOUT4L",
|
||||
"Line Out Jack", "AOUT4R",
|
||||
"AIN1L", "Line In Jack",
|
||||
"AIN1R", "Line In Jack",
|
||||
"AIN2L", "Line In Jack",
|
||||
"AIN2R", "Line In Jack";
|
||||
};
|
|
@ -18,12 +18,26 @@ Required properties:
|
|||
- pinctrl-names: Must contain a "default" entry.
|
||||
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
|
||||
See ../pinctrl/pinctrl-bindings.txt for details of the property values.
|
||||
- big-endian-regs: If this property is absent, the little endian mode will
|
||||
be in use as default, or the big endian mode will be in use for all the
|
||||
device registers.
|
||||
- big-endian-data: If this property is absent, the little endian mode will
|
||||
be in use as default, or the big endian mode will be in use for all the
|
||||
fifo data.
|
||||
- big-endian: Boolean property, required if all the FTM_PWM registers
|
||||
are big-endian rather than little-endian.
|
||||
- lsb-first: Configures whether the LSB or the MSB is transmitted first for
|
||||
the fifo data. If this property is absent, the MSB is transmitted first as
|
||||
default, or the LSB is transmitted first.
|
||||
- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
|
||||
that SAI will work in the synchronous mode (sync Tx with Rx) which means
|
||||
both the transimitter and receiver will send and receive data by following
|
||||
receiver's bit clocks and frame sync clocks.
|
||||
- fsl,sai-asynchronous: This is a boolean property. If present, indicating
|
||||
that SAI will work in the asynchronous mode, which means both transimitter
|
||||
and receiver will send and receive data by following their own bit clocks
|
||||
and frame sync clocks separately.
|
||||
|
||||
Note:
|
||||
- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
|
||||
default synchronous mode (sync Rx with Tx) will be used, which means both
|
||||
transimitter and receiver will send and receive data by following clocks
|
||||
of transimitter.
|
||||
- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
|
||||
|
||||
Example:
|
||||
sai2: sai@40031000 {
|
||||
|
@ -38,6 +52,6 @@ sai2: sai@40031000 {
|
|||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
|
||||
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
|
||||
big-endian-regs;
|
||||
big-endian-data;
|
||||
big-endian;
|
||||
lsb-first;
|
||||
};
|
||||
|
|
60
Documentation/devicetree/bindings/sound/imx-audio-es8328.txt
Normal file
60
Documentation/devicetree/bindings/sound/imx-audio-es8328.txt
Normal file
|
@ -0,0 +1,60 @@
|
|||
Freescale i.MX audio complex with ES8328 codec
|
||||
|
||||
Required properties:
|
||||
- compatible : "fsl,imx-audio-es8328"
|
||||
- model : The user-visible name of this sound complex
|
||||
- ssi-controller : The phandle of the i.MX SSI controller
|
||||
- jack-gpio : Optional GPIO for headphone jack
|
||||
- audio-amp-supply : Power regulator for speaker amps
|
||||
- audio-codec : The phandle of the ES8328 audio codec
|
||||
- audio-routing : A list of the connections between audio components.
|
||||
Each entry is a pair of strings, the first being the
|
||||
connection's sink, the second being the connection's
|
||||
source. Valid names could be power supplies, ES8328
|
||||
pins, and the jacks on the board:
|
||||
|
||||
Power supplies:
|
||||
* audio-amp
|
||||
|
||||
ES8328 pins:
|
||||
* LOUT1
|
||||
* LOUT2
|
||||
* ROUT1
|
||||
* ROUT2
|
||||
* LINPUT1
|
||||
* LINPUT2
|
||||
* RINPUT1
|
||||
* RINPUT2
|
||||
* Mic PGA
|
||||
|
||||
Board connectors:
|
||||
* Headphone
|
||||
* Speaker
|
||||
* Mic Jack
|
||||
- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
|
||||
- mux-ext-port : The external port of the i.MX audio muxer (AUDMIX)
|
||||
|
||||
Note: The AUDMUX port numbering should start at 1, which is consistent with
|
||||
hardware manual.
|
||||
|
||||
Example:
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-es8328";
|
||||
model = "imx-audio-es8328";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
jack-gpio = <&gpio5 15 0>;
|
||||
audio-amp-supply = <®_audio_amp>;
|
||||
audio-routing =
|
||||
"Speaker", "LOUT2",
|
||||
"Speaker", "ROUT2",
|
||||
"Speaker", "audio-amp",
|
||||
"Headphone", "ROUT1",
|
||||
"Headphone", "LOUT1",
|
||||
"LINPUT1", "Mic Jack",
|
||||
"RINPUT1", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
|
@ -25,6 +25,7 @@ Required properties:
|
|||
|
||||
Optional properties:
|
||||
- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
|
||||
- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
|
||||
|
||||
Example:
|
||||
|
||||
|
|
59
Documentation/devicetree/bindings/sound/rt5677.txt
Normal file
59
Documentation/devicetree/bindings/sound/rt5677.txt
Normal file
|
@ -0,0 +1,59 @@
|
|||
RT5677 audio CODEC
|
||||
|
||||
This device supports I2C only.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "realtek,rt5677".
|
||||
|
||||
- reg : The I2C address of the device.
|
||||
|
||||
- interrupts : The CODEC's interrupt output.
|
||||
|
||||
- gpio-controller : Indicates this device is a GPIO controller.
|
||||
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters (currently unused).
|
||||
|
||||
Optional properties:
|
||||
|
||||
- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
|
||||
|
||||
- realtek,in1-differential
|
||||
- realtek,in2-differential
|
||||
- realtek,lout1-differential
|
||||
- realtek,lout2-differential
|
||||
- realtek,lout3-differential
|
||||
Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential,
|
||||
rather than single-ended.
|
||||
|
||||
Pins on the device (for linking into audio routes):
|
||||
|
||||
* IN1P
|
||||
* IN1N
|
||||
* IN2P
|
||||
* IN2N
|
||||
* MICBIAS1
|
||||
* DMIC1
|
||||
* DMIC2
|
||||
* DMIC3
|
||||
* DMIC4
|
||||
* LOUT1
|
||||
* LOUT2
|
||||
* LOUT3
|
||||
|
||||
Example:
|
||||
|
||||
rt5677 {
|
||||
compatible = "realtek,rt5677";
|
||||
reg = <0x2c>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
realtek,pow-ldo2-gpio =
|
||||
<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
|
||||
realtek,in1-differential = "true";
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue