powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440
The handlers for Critical, Machine Check or Debug interrupts will save and restore MMUCR nowadays, thus we only need to disable normal interrupts when invalidating TLB entries. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -75,18 +75,19 @@ _GLOBAL(_tlbil_va)
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mfspr r5,SPRN_MMUCR
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rlwimi r5,r4,0,24,31 /* Set TID */
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/* We have to run the search with interrupts disabled, even critical
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* and debug interrupts (in fact the only critical exceptions we have
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* are debug and machine check). Otherwise an interrupt which causes
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* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
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/* We have to run the search with interrupts disabled, otherwise
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* an interrupt which causes a TLB miss can clobber the MMUCR
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* between the mtspr and the tlbsx.
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*
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* Critical and Machine Check interrupts take care of saving
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* and restoring MMUCR, so only normal interrupts have to be
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* taken care of.
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*/
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mfmsr r4
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lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
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addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
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andc r6,r4,r6
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mtmsr r6
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wrteei 0
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mtspr SPRN_MMUCR,r5
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tlbsx. r3, 0, r3
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mtmsr r4
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wrtee r4
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bne 1f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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