drivers: net: xgene: fix RGMII 10/100Mb mode
This patch fixes the RGMII 10/100M mode by reprogramming the clock. Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Tested-by: Fushen Chen <fchen@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -459,6 +459,45 @@ static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
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xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
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}
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static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
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{
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struct device *dev = &pdata->pdev->dev;
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if (dev->of_node) {
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struct clk *parent = clk_get_parent(pdata->clk);
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switch (pdata->phy_speed) {
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case SPEED_10:
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clk_set_rate(parent, 2500000);
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break;
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case SPEED_100:
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clk_set_rate(parent, 25000000);
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break;
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default:
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clk_set_rate(parent, 125000000);
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break;
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}
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}
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#ifdef CONFIG_ACPI
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else {
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switch (pdata->phy_speed) {
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case SPEED_10:
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acpi_evaluate_object(ACPI_HANDLE(dev),
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"S10", NULL, NULL);
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break;
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case SPEED_100:
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acpi_evaluate_object(ACPI_HANDLE(dev),
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"S100", NULL, NULL);
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break;
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default:
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acpi_evaluate_object(ACPI_HANDLE(dev),
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"S1G", NULL, NULL);
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break;
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}
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}
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#endif
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}
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static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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{
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struct device *dev = &pdata->pdev->dev;
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@ -477,12 +516,14 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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switch (pdata->phy_speed) {
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case SPEED_10:
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ENET_INTERFACE_MODE2_SET(&mc2, 1);
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intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
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CFG_MACMODE_SET(&icm0, 0);
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CFG_WAITASYNCRD_SET(&icm2, 500);
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rgmii &= ~CFG_SPEED_1250;
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break;
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case SPEED_100:
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ENET_INTERFACE_MODE2_SET(&mc2, 1);
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intf_ctl &= ~ENET_GHD_MODE;
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intf_ctl |= ENET_LHD_MODE;
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CFG_MACMODE_SET(&icm0, 1);
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CFG_WAITASYNCRD_SET(&icm2, 80);
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@ -490,12 +531,15 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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break;
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default:
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ENET_INTERFACE_MODE2_SET(&mc2, 2);
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intf_ctl &= ~ENET_LHD_MODE;
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intf_ctl |= ENET_GHD_MODE;
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CFG_MACMODE_SET(&icm0, 2);
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CFG_WAITASYNCRD_SET(&icm2, 0);
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if (dev->of_node) {
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CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
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CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
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}
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rgmii |= CFG_SPEED_1250;
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xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
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value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
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@ -503,7 +547,7 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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break;
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}
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mc2 |= FULL_DUPLEX2;
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mc2 |= FULL_DUPLEX2 | PAD_CRC;
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xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
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xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
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@ -522,6 +566,7 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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/* Rtype should be copied from FP */
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xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
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xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
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xgene_enet_configure_clock(pdata);
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/* Rx-Tx traffic resume */
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xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
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@ -181,6 +181,7 @@ enum xgene_enet_rm {
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#define ENET_LHD_MODE BIT(25)
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#define ENET_GHD_MODE BIT(26)
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#define FULL_DUPLEX2 BIT(0)
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#define PAD_CRC BIT(2)
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#define SCAN_AUTO_INCR BIT(5)
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#define TBYT_ADDR 0x38
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#define TPKT_ADDR 0x39
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@ -698,7 +698,6 @@ static int xgene_enet_open(struct net_device *ndev)
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else
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schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
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netif_carrier_off(ndev);
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netif_start_queue(ndev);
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return ret;
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