MIPS: disable preemption whilst initialising MSA
Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
parent
3587ea888b
commit
762a1f4388
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@ -164,8 +164,6 @@ static inline int init_fpu(void)
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{
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int ret = 0;
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preempt_disable();
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if (cpu_has_fpu) {
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ret = __own_fpu();
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if (!ret)
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@ -173,8 +171,6 @@ static inline int init_fpu(void)
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} else
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fpu_emulator_init_fpu();
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preempt_enable();
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return ret;
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}
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@ -1093,6 +1093,7 @@ static int enable_restore_fp_context(int msa)
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if (!used_math()) {
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/* First time FP context user. */
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preempt_disable();
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err = init_fpu();
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if (msa && !err) {
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enable_msa();
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@ -1100,6 +1101,7 @@ static int enable_restore_fp_context(int msa)
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set_thread_flag(TIF_USEDMSA);
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set_thread_flag(TIF_MSA_CTX_LIVE);
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}
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preempt_enable();
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if (!err)
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set_used_math();
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return err;
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@ -1139,10 +1141,11 @@ static int enable_restore_fp_context(int msa)
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* This task is using or has previously used MSA. Thus we require
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* that Status.FR == 1.
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*/
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preempt_disable();
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was_fpu_owner = is_fpu_owner();
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err = own_fpu(0);
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err = own_fpu_inatomic(0);
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if (err)
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return err;
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goto out;
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enable_msa();
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write_msa_csr(current->thread.fpu.msacsr);
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@ -1158,7 +1161,8 @@ static int enable_restore_fp_context(int msa)
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prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
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if (!prior_msa && was_fpu_owner) {
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_init_msa_upper();
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return 0;
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goto out;
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}
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if (!prior_msa) {
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@ -1182,6 +1186,10 @@ static int enable_restore_fp_context(int msa)
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if (!was_fpu_owner)
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asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31));
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}
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out:
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preempt_enable();
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return 0;
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}
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