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drm/imx/dcss: use the external 27MHz phy clock 

The 27MHz external oscillator offers a high precision low jitter clock and
is suitable for high pixel clocks modes(ie 4K@60).

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Laurentiu Palcu 2019-11-22 10:00:56 +02:00 committed by Dong Aisheng
parent b47bad65a5
commit 76c17b70c9
2 changed files with 30 additions and 6 deletions
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25
drivers/gpu/drm/imx/dcss/dcss-dev.c
View File

@ -16,6 +16,11 @@ static void dcss_clocks_enable(struct dcss_dev *dcss)
if (dcss->clks_on)
return;
if (dcss->hdmi_output) {
clk_prepare_enable(dcss->pll_phy_ref_clk);
clk_prepare_enable(dcss->pll_src_clk);
}
clk_prepare_enable(dcss->axi_clk);
clk_prepare_enable(dcss->apb_clk);
clk_prepare_enable(dcss->rtrm_clk);
@ -36,6 +41,11 @@ static void dcss_clocks_disable(struct dcss_dev *dcss)
clk_disable_unprepare(dcss->apb_clk);
clk_disable_unprepare(dcss->axi_clk);
if (dcss->hdmi_output) {
clk_disable_unprepare(dcss->pll_src_clk);
clk_disable_unprepare(dcss->pll_phy_ref_clk);
}
dcss->clks_on = false;
}
@ -111,17 +121,20 @@ static int dcss_clks_init(struct dcss_dev *dcss)
struct {
const char *id;
struct clk **clk;
bool required;
} clks[] = {
{"apb", &dcss->apb_clk},
{"axi", &dcss->axi_clk},
{"pix", &dcss->pix_clk},
{"rtrm", &dcss->rtrm_clk},
{"dtrc", &dcss->dtrc_clk},
{"apb", &dcss->apb_clk, true},
{"axi", &dcss->axi_clk, true},
{"pix", &dcss->pix_clk, true},
{"rtrm", &dcss->rtrm_clk, true},
{"dtrc", &dcss->dtrc_clk, true},
{"pll_src", &dcss->pll_src_clk, dcss->hdmi_output},
{"pll_phy_ref", &dcss->pll_phy_ref_clk, dcss->hdmi_output},
};
for (i = 0; i < ARRAY_SIZE(clks); i++) {
*clks[i].clk = devm_clk_get(dcss->dev, clks[i].id);
if (IS_ERR(*clks[i].clk)) {
if (IS_ERR(*clks[i].clk) && clks[i].required) {
dev_err(dcss->dev, "failed to get %s clock\n",
clks[i].id);
return PTR_ERR(*clks[i].clk);

11
drivers/gpu/drm/imx/dcss/dcss-dtg.c
View File

@ -82,6 +82,7 @@ struct dcss_dtg {
u32 ctx_id;
bool in_use;
bool hdmi_output;
u32 dis_ulc_x;
u32 dis_ulc_y;
@ -170,6 +171,7 @@ int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base)
dcss->dtg = dtg;
dtg->dev = dcss->dev;
dtg->ctxld = dcss->ctxld;
dtg->hdmi_output = dcss->hdmi_output;
dtg->base_reg = devm_ioremap(dcss->dev, dtg_base, SZ_4K);
if (!dtg->base_reg) {
@ -238,6 +240,15 @@ void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
vm->vactive - 1;
clk_disable_unprepare(dtg->pix_clk);
if (dtg->hdmi_output) {
int err;
clk_disable_unprepare(dtg->pll_src_clk);
err = clk_set_parent(dtg->pll_src_clk, dtg->pll_phy_ref_clk);
if (err < 0)
dev_warn(dtg->dev, "clk_set_parent() returned %d", err);
clk_prepare_enable(dtg->pll_src_clk);
}
clk_set_rate(dtg->pix_clk, vm->pixelclock);
clk_prepare_enable(dtg->pix_clk);