net/mlx5: EQ, Generic EQ
Add mlx5_eq_{create/destroy}_generic APIs and EQE access methods, for
mlx5 core consumers generic EQs.
This API will be used in downstream patch to move page fault (RDMA ODP)
EQ logic into mlx5_ib rdma driver, hence it will use a generic EQ.
Current mlx5 EQ allocation scheme:
On load mlx5 allocates 4 (for async) + #cores (for data completions)
MSIX vectors, mlx5 core will assign 3 MSIX vectors for internal async
EQs and will use all of the #cores MSIX vectors for completion EQs,
(One vector is going to be reserved for a generic EQ).
After this patch an external user (e.g mlx5_ib) of mlx5_core
can use this new API to create new generic EQs with the reserved msix
vector index for that eq.
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
This commit is contained in:
Saeed Mahameed
Leon Romanovsky
parent
16d760839c
commit
7701707cb9
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@ -33,6 +33,7 @@
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/eq.h>
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#include <linux/mlx5/cmd.h>
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#ifdef CONFIG_RFS_ACCEL
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#include <linux/cpu_rmap.h>
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@ -69,6 +70,7 @@ enum {
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struct mlx5_irq_info {
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cpumask_var_t mask;
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char name[MLX5_MAX_IRQ_NAME];
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void *context; /* dev_id provided to request_irq */
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};
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struct mlx5_eq_table {
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@ -81,7 +83,6 @@ struct mlx5_eq_table {
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struct mlx5_eq_pagefault pfault_eq;
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#endif
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struct mutex lock; /* sync async eqs creations */
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u8 num_async_eqs;
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int num_comp_vectors;
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struct mlx5_irq_info *irq_info;
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#ifdef CONFIG_RFS_ACCEL
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@ -229,19 +230,19 @@ static void eqe_pf_action(struct work_struct *work)
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work);
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struct mlx5_eq_pagefault *eq = pfault->eq;
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mlx5_core_page_fault(eq->core.dev, pfault);
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mlx5_core_page_fault(eq->core->dev, pfault);
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mempool_free(pfault, eq->pool);
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}
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static void eq_pf_process(struct mlx5_eq_pagefault *eq)
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{
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struct mlx5_core_dev *dev = eq->core.dev;
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struct mlx5_core_dev *dev = eq->core->dev;
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struct mlx5_eqe_page_fault *pf_eqe;
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struct mlx5_pagefault *pfault;
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struct mlx5_eqe *eqe;
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int set_ci = 0;
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while ((eqe = next_eqe_sw(&eq->core))) {
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while ((eqe = next_eqe_sw(eq->core))) {
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pfault = mempool_alloc(eq->pool, GFP_ATOMIC);
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if (!pfault) {
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schedule_work(&eq->work);
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@ -316,16 +317,16 @@ static void eq_pf_process(struct mlx5_eq_pagefault *eq)
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INIT_WORK(&pfault->work, eqe_pf_action);
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queue_work(eq->wq, &pfault->work);
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++eq->core.cons_index;
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++eq->core->cons_index;
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++set_ci;
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if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
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eq_update_ci(&eq->core, 0);
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eq_update_ci(eq->core, 0);
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set_ci = 0;
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}
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}
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eq_update_ci(&eq->core, 1);
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eq_update_ci(eq->core, 1);
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}
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static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
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@ -368,6 +369,7 @@ static void eq_pf_action(struct work_struct *work)
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static int
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create_pf_eq(struct mlx5_core_dev *dev, struct mlx5_eq_pagefault *eq)
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{
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struct mlx5_eq_param param = {};
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int err;
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spin_lock_init(&eq->lock);
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@ -386,11 +388,19 @@ create_pf_eq(struct mlx5_core_dev *dev, struct mlx5_eq_pagefault *eq)
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goto err_mempool;
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}
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err = mlx5_create_async_eq(dev, &eq->core, MLX5_NUM_ASYNC_EQE,
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1 << MLX5_EVENT_TYPE_PAGE_FAULT,
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"mlx5_page_fault_eq", mlx5_eq_pf_int);
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if (err)
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param = (struct mlx5_eq_param) {
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.index = MLX5_EQ_PFAULT_IDX,
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.mask = 1 << MLX5_EVENT_TYPE_PAGE_FAULT,
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.nent = MLX5_NUM_ASYNC_EQE,
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.context = eq,
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.handler = mlx5_eq_pf_int
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};
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eq->core = mlx5_eq_create_generic(dev, "mlx5_page_fault_eq", ¶m);
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if (IS_ERR(eq->core)) {
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err = PTR_ERR(eq->core);
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goto err_wq;
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}
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return 0;
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err_wq:
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@ -404,7 +414,7 @@ static int destroy_pf_eq(struct mlx5_core_dev *dev, struct mlx5_eq_pagefault *eq
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{
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int err;
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err = mlx5_destroy_async_eq(dev, &eq->core);
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err = mlx5_eq_destroy_generic(dev, eq->core);
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cancel_work_sync(&eq->work);
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destroy_workqueue(eq->wq);
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mempool_destroy(eq->pool);
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@ -710,25 +720,29 @@ static void init_eq_buf(struct mlx5_eq *eq)
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}
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static int
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mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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int nent, u64 mask, const char *name, irq_handler_t handler)
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create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, const char *name,
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struct mlx5_eq_param *param)
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{
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struct mlx5_eq_table *eq_table = dev->priv.eq_table;
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struct mlx5_cq_table *cq_table = &eq->cq_table;
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u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
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struct mlx5_priv *priv = &dev->priv;
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u8 vecidx = param->index;
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__be64 *pas;
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void *eqc;
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int inlen;
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u32 *in;
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int err;
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if (eq_table->irq_info[vecidx].context)
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return -EEXIST;
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/* Init CQ table */
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memset(cq_table, 0, sizeof(*cq_table));
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spin_lock_init(&cq_table->lock);
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INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
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eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
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eq->nent = roundup_pow_of_two(param->nent + MLX5_NUM_SPARE_EQE);
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eq->cons_index = 0;
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err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
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if (err)
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@ -749,7 +763,7 @@ mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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mlx5_fill_page_array(&eq->buf, pas);
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MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
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MLX5_SET64(create_eq_in, in, event_bitmask, mask);
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MLX5_SET64(create_eq_in, in, event_bitmask, param->mask);
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eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
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MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
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@ -764,13 +778,15 @@ mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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snprintf(eq_table->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
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name, pci_name(dev->pdev));
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eq_table->irq_info[vecidx].context = param->context;
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eq->vecidx = vecidx;
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eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
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eq->irqn = pci_irq_vector(dev->pdev, vecidx);
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eq->dev = dev;
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eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
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err = request_irq(eq->irqn, handler, 0,
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eq_table->irq_info[vecidx].name, eq);
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err = request_irq(eq->irqn, param->handler, 0,
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eq_table->irq_info[vecidx].name, param->context);
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if (err)
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goto err_eq;
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@ -799,12 +815,19 @@ err_buf:
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return err;
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}
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static int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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static int destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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{
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struct mlx5_eq_table *eq_table = dev->priv.eq_table;
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struct mlx5_irq_info *irq_info;
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int err;
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irq_info = &eq_table->irq_info[eq->vecidx];
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mlx5_debug_eq_remove(dev, eq);
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free_irq(eq->irqn, eq);
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free_irq(eq->irqn, irq_info->context);
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irq_info->context = NULL;
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err = mlx5_cmd_destroy_eq(dev, eq->eqn);
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if (err)
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mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
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@ -883,48 +906,38 @@ void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev)
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/* Async EQs */
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int mlx5_create_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
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int nent, u64 mask, const char *name, irq_handler_t handler)
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static int create_async_eq(struct mlx5_core_dev *dev, const char *name,
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struct mlx5_eq *eq, struct mlx5_eq_param *param)
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{
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struct mlx5_eq_table *eq_table = dev->priv.eq_table;
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u8 vecdix;
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int err;
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mutex_lock(&eq_table->lock);
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if (eq_table->num_async_eqs >= MLX5_EQ_MAX_ASYNC_EQS) {
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if (param->index >= MLX5_EQ_MAX_ASYNC_EQS) {
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err = -ENOSPC;
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goto unlock;
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}
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vecdix = eq_table->num_async_eqs + 1;
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err = mlx5_create_map_eq(dev, eq, vecdix, nent, mask, name, handler);
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if (!err)
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eq_table->num_async_eqs++;
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err = create_map_eq(dev, eq, name, param);
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unlock:
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mutex_unlock(&eq_table->lock);
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return err;
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}
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int mlx5_destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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static int destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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{
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struct mlx5_eq_table *eq_table = dev->priv.eq_table;
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int err;
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mutex_lock(&eq_table->lock);
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err = mlx5_destroy_unmap_eq(dev, eq);
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if (!err)
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eq_table->num_async_eqs--;
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err = destroy_unmap_eq(dev, eq);
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mutex_unlock(&eq_table->lock);
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return err;
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}
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static int create_async_eqs(struct mlx5_core_dev *dev)
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static u64 gather_async_events_mask(struct mlx5_core_dev *dev)
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{
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struct mlx5_eq_table *table = dev->priv.eq_table;
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u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
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int err;
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if (MLX5_VPORT_MANAGER(dev))
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
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@ -953,9 +966,23 @@ static int create_async_eqs(struct mlx5_core_dev *dev)
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if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
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async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
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err = mlx5_create_async_eq(dev, &table->cmd_eq, MLX5_NUM_CMD_EQE,
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1ull << MLX5_EVENT_TYPE_CMD, "mlx5_cmd_eq",
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mlx5_eq_async_int);
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return async_event_mask;
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}
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static int create_async_eqs(struct mlx5_core_dev *dev)
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{
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struct mlx5_eq_table *table = dev->priv.eq_table;
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struct mlx5_eq_param param = {};
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int err;
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param = (struct mlx5_eq_param) {
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.index = MLX5_EQ_CMD_IDX,
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.mask = 1ull << MLX5_EVENT_TYPE_CMD,
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.nent = MLX5_NUM_CMD_EQE,
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.context = &table->cmd_eq,
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.handler = mlx5_eq_async_int,
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};
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err = create_async_eq(dev, "mlx5_cmd_eq", &table->cmd_eq, ¶m);
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if (err) {
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mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
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return err;
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@ -963,15 +990,27 @@ static int create_async_eqs(struct mlx5_core_dev *dev)
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mlx5_cmd_use_events(dev);
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err = mlx5_create_async_eq(dev, &table->async_eq, MLX5_NUM_ASYNC_EQE,
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async_event_mask, "mlx5_async_eq", mlx5_eq_async_int);
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param = (struct mlx5_eq_param) {
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.index = MLX5_EQ_ASYNC_IDX,
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.mask = gather_async_events_mask(dev),
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.nent = MLX5_NUM_ASYNC_EQE,
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.context = &table->async_eq,
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.handler = mlx5_eq_async_int,
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};
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err = create_async_eq(dev, "mlx5_async_eq", &table->async_eq, ¶m);
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if (err) {
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mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
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goto err1;
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}
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err = mlx5_create_async_eq(dev, &table->pages_eq, /* TODO: sriov max_vf + */ 1,
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1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", mlx5_eq_async_int);
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param = (struct mlx5_eq_param) {
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.index = MLX5_EQ_PAGEREQ_IDX,
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.mask = 1 << MLX5_EVENT_TYPE_PAGE_REQUEST,
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.nent = /* TODO: sriov max_vf + */ 1,
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.context = &table->pages_eq,
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.handler = mlx5_eq_async_int,
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};
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err = create_async_eq(dev, "mlx5_pages_eq", &table->pages_eq, ¶m);
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if (err) {
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mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
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goto err2;
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@ -989,17 +1028,17 @@ static int create_async_eqs(struct mlx5_core_dev *dev)
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return err;
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err3:
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mlx5_destroy_async_eq(dev, &table->pages_eq);
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destroy_async_eq(dev, &table->pages_eq);
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#else
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return err;
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#endif
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err2:
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mlx5_destroy_async_eq(dev, &table->async_eq);
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destroy_async_eq(dev, &table->async_eq);
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err1:
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mlx5_cmd_use_polling(dev);
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mlx5_destroy_async_eq(dev, &table->cmd_eq);
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destroy_async_eq(dev, &table->cmd_eq);
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return err;
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}
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@ -1017,18 +1056,18 @@ static void destroy_async_eqs(struct mlx5_core_dev *dev)
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}
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#endif
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err = mlx5_destroy_async_eq(dev, &table->pages_eq);
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err = destroy_async_eq(dev, &table->pages_eq);
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if (err)
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mlx5_core_err(dev, "failed to destroy pages eq, err(%d)\n",
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err);
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err = mlx5_destroy_async_eq(dev, &table->async_eq);
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err = destroy_async_eq(dev, &table->async_eq);
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if (err)
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mlx5_core_err(dev, "failed to destroy async eq, err(%d)\n",
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err);
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mlx5_cmd_use_polling(dev);
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err = mlx5_destroy_async_eq(dev, &table->cmd_eq);
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err = destroy_async_eq(dev, &table->cmd_eq);
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if (err)
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mlx5_core_err(dev, "failed to destroy command eq, err(%d)\n",
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err);
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@ -1049,6 +1088,77 @@ void mlx5_eq_synchronize_cmd_irq(struct mlx5_core_dev *dev)
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synchronize_irq(dev->priv.eq_table->cmd_eq.irqn);
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}
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/* Generic EQ API for mlx5_core consumers
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* Needed For RDMA ODP EQ for now
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*/
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struct mlx5_eq *
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mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name,
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struct mlx5_eq_param *param)
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{
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struct mlx5_eq *eq = kvzalloc(sizeof(*eq), GFP_KERNEL);
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int err;
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if (!eq)
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return ERR_PTR(-ENOMEM);
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err = create_async_eq(dev, name, eq, param);
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if (err) {
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kvfree(eq);
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eq = ERR_PTR(err);
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}
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return eq;
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}
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EXPORT_SYMBOL(mlx5_eq_create_generic);
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int mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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{
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int err;
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if (IS_ERR(eq))
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return -EINVAL;
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err = destroy_async_eq(dev, eq);
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if (err)
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goto out;
|
||||
|
||||
kvfree(eq);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_eq_destroy_generic);
|
||||
|
||||
struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc)
|
||||
{
|
||||
u32 ci = eq->cons_index + cc;
|
||||
struct mlx5_eqe *eqe;
|
||||
|
||||
eqe = get_eqe(eq, ci & (eq->nent - 1));
|
||||
eqe = ((eqe->owner & 1) ^ !!(ci & eq->nent)) ? NULL : eqe;
|
||||
/* Make sure we read EQ entry contents after we've
|
||||
* checked the ownership bit.
|
||||
*/
|
||||
if (eqe)
|
||||
dma_rmb();
|
||||
|
||||
return eqe;
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_eq_get_eqe);
|
||||
|
||||
void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
|
||||
{
|
||||
__be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
|
||||
u32 val;
|
||||
|
||||
eq->cons_index += cc;
|
||||
val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
|
||||
|
||||
__raw_writel((__force u32)cpu_to_be32(val), addr);
|
||||
/* We still want ordering, just not swabbing, so add a barrier */
|
||||
mb();
|
||||
}
|
||||
EXPORT_SYMBOL(mlx5_eq_update_ci);
|
||||
|
||||
/* Completion EQs */
|
||||
|
||||
static int set_comp_irq_affinity_hint(struct mlx5_core_dev *mdev, int i)
|
||||
|
|
@ -1127,7 +1237,7 @@ static void destroy_comp_eqs(struct mlx5_core_dev *dev)
|
|||
#endif
|
||||
list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
|
||||
list_del(&eq->list);
|
||||
if (mlx5_destroy_unmap_eq(dev, &eq->core))
|
||||
if (destroy_unmap_eq(dev, &eq->core))
|
||||
mlx5_core_warn(dev, "failed to destroy comp EQ 0x%x\n",
|
||||
eq->core.eqn);
|
||||
tasklet_disable(&eq->tasklet_ctx.task);
|
||||
|
|
@ -1155,6 +1265,7 @@ static int create_comp_eqs(struct mlx5_core_dev *dev)
|
|||
#endif
|
||||
for (i = 0; i < ncomp_vec; i++) {
|
||||
int vecidx = i + MLX5_EQ_VEC_COMP_BASE;
|
||||
struct mlx5_eq_param param = {};
|
||||
|
||||
eq = kzalloc(sizeof(*eq), GFP_KERNEL);
|
||||
if (!eq) {
|
||||
|
|
@ -1172,8 +1283,14 @@ static int create_comp_eqs(struct mlx5_core_dev *dev)
|
|||
irq_cpu_rmap_add(table->rmap, pci_irq_vector(dev->pdev, vecidx));
|
||||
#endif
|
||||
snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
|
||||
err = mlx5_create_map_eq(dev, &eq->core, vecidx, nent, 0,
|
||||
name, mlx5_eq_comp_int);
|
||||
param = (struct mlx5_eq_param) {
|
||||
.index = vecidx,
|
||||
.mask = 0,
|
||||
.nent = nent,
|
||||
.context = &eq->core,
|
||||
.handler = mlx5_eq_comp_int
|
||||
};
|
||||
err = create_map_eq(dev, &eq->core, name, ¶m);
|
||||
if (err) {
|
||||
kfree(eq);
|
||||
goto clean;
|
||||
|
|
@ -1257,7 +1374,7 @@ struct mlx5_eq_comp *mlx5_eqn2comp_eq(struct mlx5_core_dev *dev, int eqn)
|
|||
void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
|
||||
{
|
||||
struct mlx5_eq_table *table = dev->priv.eq_table;
|
||||
struct mlx5_eq_comp *eq;
|
||||
int i, max_eqs;
|
||||
|
||||
clear_comp_irqs_affinity_hints(dev);
|
||||
|
||||
|
|
@ -1267,16 +1384,16 @@ void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
|
|||
table->rmap = NULL;
|
||||
}
|
||||
#endif
|
||||
list_for_each_entry(eq, &table->comp_eqs_list, list)
|
||||
free_irq(eq->core.irqn, eq);
|
||||
|
||||
free_irq(table->pages_eq.irqn, &table->pages_eq);
|
||||
free_irq(table->async_eq.irqn, &table->async_eq);
|
||||
free_irq(table->cmd_eq.irqn, &table->cmd_eq);
|
||||
#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
|
||||
if (MLX5_CAP_GEN(dev, pg))
|
||||
free_irq(table->pfault_eq.core.irqn, &table->pfault_eq.core);
|
||||
#endif
|
||||
mutex_lock(&table->lock); /* sync with create/destroy_async_eq */
|
||||
max_eqs = table->num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
|
||||
for (i = max_eqs - 1; i >= 0; i--) {
|
||||
if (!table->irq_info[i].context)
|
||||
continue;
|
||||
free_irq(pci_irq_vector(dev->pdev, i), table->irq_info[i].context);
|
||||
table->irq_info[i].context = NULL;
|
||||
}
|
||||
mutex_unlock(&table->lock);
|
||||
pci_free_irq_vectors(dev->pdev);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -7,11 +7,6 @@
|
|||
|
||||
#define MLX5_MAX_IRQ_NAME (32)
|
||||
|
||||
enum {
|
||||
MLX5_EQ_MAX_ASYNC_EQS = 4, /* mlx5_core needs at least 3 */
|
||||
MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS,
|
||||
};
|
||||
|
||||
struct mlx5_eq_tasklet {
|
||||
struct list_head list;
|
||||
struct list_head process_list;
|
||||
|
|
@ -31,6 +26,7 @@ struct mlx5_eq {
|
|||
u32 cons_index;
|
||||
struct mlx5_frag_buf buf;
|
||||
int size;
|
||||
unsigned int vecidx;
|
||||
unsigned int irqn;
|
||||
u8 eqn;
|
||||
int nent;
|
||||
|
|
@ -44,7 +40,7 @@ struct mlx5_eq_comp {
|
|||
};
|
||||
|
||||
struct mlx5_eq_pagefault {
|
||||
struct mlx5_eq core; /* Must be first */
|
||||
struct mlx5_eq *core;
|
||||
struct work_struct work;
|
||||
spinlock_t lock; /* Pagefaults spinlock */
|
||||
struct workqueue_struct *wq;
|
||||
|
|
@ -55,10 +51,6 @@ int mlx5_eq_table_init(struct mlx5_core_dev *dev);
|
|||
void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev);
|
||||
int mlx5_eq_table_create(struct mlx5_core_dev *dev);
|
||||
void mlx5_eq_table_destroy(struct mlx5_core_dev *dev);
|
||||
int mlx5_create_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
|
||||
int nent, u64 mask, const char *name,
|
||||
irq_handler_t handler);
|
||||
int mlx5_destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
|
||||
|
||||
int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq);
|
||||
int mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq);
|
||||
|
|
|
|||
39
include/linux/mlx5/eq.h
Normal file
39
include/linux/mlx5/eq.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
|
||||
/* Copyright (c) 2018 Mellanox Technologies. */
|
||||
|
||||
#ifndef MLX5_CORE_EQ_H
|
||||
#define MLX5_CORE_EQ_H
|
||||
|
||||
#include <linux/mlx5/driver.h>
|
||||
|
||||
enum {
|
||||
MLX5_EQ_PAGEREQ_IDX = 0,
|
||||
MLX5_EQ_CMD_IDX = 1,
|
||||
MLX5_EQ_ASYNC_IDX = 2,
|
||||
/* reserved to be used by mlx5_core ulps (mlx5e/mlx5_ib) */
|
||||
MLX5_EQ_PFAULT_IDX = 3,
|
||||
MLX5_EQ_MAX_ASYNC_EQS,
|
||||
/* completion eqs vector indices start here */
|
||||
MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS,
|
||||
};
|
||||
|
||||
struct mlx5_eq;
|
||||
|
||||
struct mlx5_eq_param {
|
||||
u8 index;
|
||||
int nent;
|
||||
u64 mask;
|
||||
void *context;
|
||||
irq_handler_t handler;
|
||||
};
|
||||
|
||||
struct mlx5_eq *
|
||||
mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name,
|
||||
struct mlx5_eq_param *param);
|
||||
int
|
||||
mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
|
||||
|
||||
struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
|
||||
void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
|
||||
|
||||
#endif /* MLX5_CORE_EQ_H */
|
||||
Loading…
Reference in a new issue