[media] v4l: vsp1: Enable display list support for the HS[IT], LUT, SRU and UDS

Those modules were left out of display list integration as they're not
used by the DRM pipeline. To prepare for display list support in non-DRM
pipelines use the module write API to set registers.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Laurent Pinchart 2015-11-01 12:26:14 -02:00 committed by Mauro Carvalho Chehab
parent 59d0b2bf1d
commit 773abafe6f
4 changed files with 5 additions and 5 deletions

View file

@ -28,7 +28,7 @@
static inline void vsp1_hsit_write(struct vsp1_hsit *hsit, u32 reg, u32 data)
{
vsp1_write(hsit->entity.vsp1, reg, data);
vsp1_mod_write(&hsit->entity, reg, data);
}
/* -----------------------------------------------------------------------------

View file

@ -29,7 +29,7 @@
static inline void vsp1_lut_write(struct vsp1_lut *lut, u32 reg, u32 data)
{
vsp1_write(lut->entity.vsp1, reg, data);
vsp1_mod_write(&lut->entity, reg, data);
}
/* -----------------------------------------------------------------------------

View file

@ -28,7 +28,7 @@
static inline void vsp1_sru_write(struct vsp1_sru *sru, u32 reg, u32 data)
{
vsp1_write(sru->entity.vsp1, reg, data);
vsp1_mod_write(&sru->entity, reg, data);
}
/* -----------------------------------------------------------------------------

View file

@ -31,8 +31,8 @@
static inline void vsp1_uds_write(struct vsp1_uds *uds, u32 reg, u32 data)
{
vsp1_write(uds->entity.vsp1,
reg + uds->entity.index * VI6_UDS_OFFSET, data);
vsp1_mod_write(&uds->entity, reg + uds->entity.index * VI6_UDS_OFFSET,
data);
}
/* -----------------------------------------------------------------------------