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ALSA: hda - Rename reg access ops in hda_controller_ops

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Using readl, writel, etc. resulted in some architectures, such as
s390, expanding the member names into zpci_writel.  Obviously not the
intended result.

Fixes s390 build breakage introduced by "4083081 - ALSA: hda - Allow
different ops to read/write registers"

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Dylan Reid 2014-03-02 20:44:00 -08:00 committed by Takashi Iwai
parent 7c3e438add
commit 778bde6f59
2 changed files with 24 additions and 24 deletions
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12
sound/pci/hda/hda_intel.c
View file

@ -1537,12 +1537,12 @@ static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
}
static const struct hda_controller_ops pci_hda_ops = {
.writel = pci_azx_writel,
.readl = pci_azx_readl,
.writew = pci_azx_writew,
.readw = pci_azx_readw,
.writeb = pci_azx_writeb,
.readb = pci_azx_readb,
.reg_writel = pci_azx_writel,
.reg_readl = pci_azx_readl,
.reg_writew = pci_azx_writew,
.reg_readw = pci_azx_readw,
.reg_writeb = pci_azx_writeb,
.reg_readb = pci_azx_readb,
.disable_msi_reset_irq = disable_msi_reset_irq,
.dma_alloc_pages = dma_alloc_pages,
.dma_free_pages = dma_free_pages,

36
sound/pci/hda/hda_priv.h
View file

@ -290,12 +290,12 @@ struct azx;
/* Functions to read/write to hda registers. */
struct hda_controller_ops {
/* Register Access */
void (*writel)(u32 value, u32 *addr);
u32 (*readl)(u32 *addr);
void (*writew)(u16 value, u16 *addr);
u16 (*readw)(u16 *addr);
void (*writeb)(u8 value, u8 *addr);
u8 (*readb)(u8 *addr);
void (*reg_writel)(u32 value, u32 *addr);
u32 (*reg_readl)(u32 *addr);
void (*reg_writew)(u16 value, u16 *addr);
u16 (*reg_readw)(u16 *addr);
void (*reg_writeb)(u8 value, u8 *addr);
u8 (*reg_readb)(u8 *addr);
/* Disable msi if supported, PCI only */
int (*disable_msi_reset_irq)(struct azx *);
/* Allocation ops */
@ -435,29 +435,29 @@ struct azx {
*/
#define azx_writel(chip, reg, value) \
((chip)->ops->writel(value, (chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readl(chip, reg) \
((chip)->ops->readl((chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg))
#define azx_writew(chip, reg, value) \
((chip)->ops->writew(value, (chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readw(chip, reg) \
((chip)->ops->readw((chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg))
#define azx_writeb(chip, reg, value) \
((chip)->ops->writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readb(chip, reg) \
((chip)->ops->readb((chip)->remap_addr + ICH6_REG_##reg))
((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg))
#define azx_sd_writel(chip, dev, reg, value) \
((chip)->ops->writel(value, (dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readl(chip, dev, reg) \
((chip)->ops->readl((dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_writew(chip, dev, reg, value) \
((chip)->ops->writew(value, (dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readw(chip, dev, reg) \
((chip)->ops->readw((dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_writeb(chip, dev, reg, value) \
((chip)->ops->writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readb(chip, dev, reg) \
((chip)->ops->readb((dev)->sd_addr + ICH6_REG_##reg))
((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg))
#endif /* __SOUND_HDA_PRIV_H */