crypto: atmel-aes - Fix counter overflow in CTR mode
32 bit counter is not supported by neither of our AES IPs, all implement
a 16 bit block counter. Drop the 32 bit block counter logic.
Fixes: fcac83656a
("crypto: atmel-aes - fix the counter overflow in CTR mode")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -88,7 +88,6 @@
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struct atmel_aes_caps {
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bool has_dualbuff;
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bool has_cfb64;
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bool has_ctr32;
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bool has_gcm;
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bool has_xts;
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bool has_authenc;
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@ -1018,8 +1017,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
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struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
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struct skcipher_request *req = skcipher_request_cast(dd->areq);
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struct scatterlist *src, *dst;
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u32 ctr, blocks;
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size_t datalen;
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u32 ctr;
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u16 blocks, start, end;
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bool use_dma, fragmented = false;
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/* Check for transfer completion. */
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@ -1031,27 +1031,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
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datalen = req->cryptlen - ctx->offset;
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blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
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ctr = be32_to_cpu(ctx->iv[3]);
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if (dd->caps.has_ctr32) {
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/* Check 32bit counter overflow. */
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u32 start = ctr;
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u32 end = start + blocks - 1;
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if (end < start) {
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ctr |= 0xffffffff;
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datalen = AES_BLOCK_SIZE * -start;
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fragmented = true;
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}
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} else {
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/* Check 16bit counter overflow. */
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u16 start = ctr & 0xffff;
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u16 end = start + (u16)blocks - 1;
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/* Check 16bit counter overflow. */
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start = ctr & 0xffff;
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end = start + blocks - 1;
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if (blocks >> 16 || end < start) {
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ctr |= 0xffff;
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datalen = AES_BLOCK_SIZE * (0x10000-start);
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fragmented = true;
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}
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if (blocks >> 16 || end < start) {
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ctr |= 0xffff;
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datalen = AES_BLOCK_SIZE * (0x10000 - start);
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fragmented = true;
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}
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use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
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/* Jump to offset. */
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@ -2521,7 +2511,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
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{
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dd->caps.has_dualbuff = 0;
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dd->caps.has_cfb64 = 0;
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dd->caps.has_ctr32 = 0;
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dd->caps.has_gcm = 0;
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dd->caps.has_xts = 0;
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dd->caps.has_authenc = 0;
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@ -2532,7 +2521,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
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case 0x500:
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dd->caps.has_dualbuff = 1;
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dd->caps.has_cfb64 = 1;
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dd->caps.has_ctr32 = 1;
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dd->caps.has_gcm = 1;
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dd->caps.has_xts = 1;
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dd->caps.has_authenc = 1;
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@ -2541,7 +2529,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
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case 0x200:
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dd->caps.has_dualbuff = 1;
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dd->caps.has_cfb64 = 1;
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dd->caps.has_ctr32 = 1;
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dd->caps.has_gcm = 1;
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dd->caps.max_burst_size = 4;
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break;
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