[MIPS] VSMP: Fix initialization ordering bug.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Ralf Baechle
parent
3ab0f40f33
commit
781b0f8d4f
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@ -140,15 +140,88 @@ static struct irqaction irq_call = {
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.name = "IPI_call"
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};
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static void __init smp_copy_vpe_config(void)
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{
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write_vpe_c0_status(
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(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
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/* set config to be the same as vpe0, particularly kseg0 coherency alg */
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write_vpe_c0_config( read_c0_config());
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/* make sure there are no software interrupts pending */
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write_vpe_c0_cause(0);
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/* Propagate Config7 */
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write_vpe_c0_config7(read_c0_config7());
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}
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static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
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unsigned int ncpu)
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{
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if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
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return ncpu;
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/* Deactivate all but VPE 0 */
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if (tc != 0) {
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unsigned long tmp = read_vpe_c0_vpeconf0();
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tmp &= ~VPECONF0_VPA;
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/* master VPE */
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tmp |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(tmp);
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/* Record this as available CPU */
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cpu_set(tc, phys_cpu_present_map);
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__cpu_number_map[tc] = ++ncpu;
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__cpu_logical_map[ncpu] = tc;
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}
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/* Disable multi-threading with TC's */
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write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
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if (tc != 0)
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smp_copy_vpe_config();
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return ncpu;
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}
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static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
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{
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unsigned long tmp;
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if (!tc)
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return;
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/* bind a TC to each VPE, May as well put all excess TC's
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on the last VPE */
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if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
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write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
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else {
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write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
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/* and set XTC */
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write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
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}
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tmp = read_tc_c0_tcstatus();
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/* mark not allocated and not dynamically allocatable */
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tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
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tmp |= TCSTATUS_IXMT; /* interrupt exempt */
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write_tc_c0_tcstatus(tmp);
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write_tc_c0_tchalt(TCHALT_H);
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}
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/*
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* Common setup before any secondaries are started
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* Make sure all CPU's are in a sensible state before we boot any of the
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* secondarys
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*/
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void plat_smp_setup(void)
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void __init plat_smp_setup(void)
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{
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unsigned long val;
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int i, num;
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unsigned int mvpconf0, ntc, tc, ncpu = 0;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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@ -167,75 +240,16 @@ void plat_smp_setup(void)
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/* Put MVPE's into 'configuration state' */
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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val = read_c0_mvpconf0();
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mvpconf0 = read_c0_mvpconf0();
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ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
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/* we'll always have more TC's than VPE's, so loop setting everything
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to a sensible state */
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for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
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settc(i);
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for (tc = 0; tc <= ntc; tc++) {
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settc(tc);
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/* VPE's */
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if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
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/* deactivate all but vpe0 */
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if (i != 0) {
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unsigned long tmp = read_vpe_c0_vpeconf0();
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tmp &= ~VPECONF0_VPA;
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/* master VPE */
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tmp |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(tmp);
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/* Record this as available CPU */
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cpu_set(i, phys_cpu_present_map);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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/* disable multi-threading with TC's */
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write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
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if (i != 0) {
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write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
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/* set config to be the same as vpe0, particularly kseg0 coherency alg */
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write_vpe_c0_config( read_c0_config());
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/* make sure there are no software interrupts pending */
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write_vpe_c0_cause(0);
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/* Propagate Config7 */
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write_vpe_c0_config7(read_c0_config7());
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}
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}
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/* TC's */
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if (i != 0) {
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unsigned long tmp;
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/* bind a TC to each VPE, May as well put all excess TC's
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on the last VPE */
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if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
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write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
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else {
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write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
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/* and set XTC */
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write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
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}
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tmp = read_tc_c0_tcstatus();
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/* mark not allocated and not dynamically allocatable */
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tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
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tmp |= TCSTATUS_IXMT; /* interrupt exempt */
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write_tc_c0_tcstatus(tmp);
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write_tc_c0_tchalt(TCHALT_H);
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}
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smp_tc_init(tc, mvpconf0);
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ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
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}
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/* Release config state */
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@ -243,7 +257,7 @@ void plat_smp_setup(void)
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/* We'll wait until starting the secondaries before starting MVPE */
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
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}
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void __init plat_prepare_cpus(unsigned int max_cpus)
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