clk: ti: dra7: fix parent for gmac_clkctrl
[ Upstream commit5.4-rM2-2.2.x-imx-squashed69e3002837
] The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation. Hence, fix it. Fixes:dffa9051d5
('clk: ti: dra7: add new clkctrl data') Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
parent
2d7fa7564b
commit
7828a927b8
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@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
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};
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static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
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{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
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{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
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{ 0 },
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};
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