C6X: cache control
Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Aurelien Jacquiot
Mark Salter
parent
81ec988981
commit
784bdcd0aa
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@ -0,0 +1,90 @@
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/*
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* Port on Texas Instruments TMS320C6x architecture
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*
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* Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
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* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_C6X_CACHE_H
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#define _ASM_C6X_CACHE_H
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#include <linux/irqflags.h>
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/*
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* Cache line size
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*/
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#define L1D_CACHE_BYTES 64
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#define L1P_CACHE_BYTES 32
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#define L2_CACHE_BYTES 128
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/*
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* L2 used as cache
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*/
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#define L2MODE_SIZE L2MODE_256K_CACHE
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/*
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* For practical reasons the L1_CACHE_BYTES defines should not be smaller than
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* the L2 line size
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*/
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#define L1_CACHE_BYTES L2_CACHE_BYTES
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#define L2_CACHE_ALIGN_LOW(x) \
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(((x) & ~(L2_CACHE_BYTES - 1)))
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#define L2_CACHE_ALIGN_UP(x) \
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(((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
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#define L2_CACHE_ALIGN_CNT(x) \
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(((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
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/*
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* This is the granularity of hardware cacheability control.
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*/
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#define CACHEABILITY_ALIGN 0x01000000
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/*
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* Align a physical address to MAR regions
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*/
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#define CACHE_REGION_START(v) \
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(((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
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#define CACHE_REGION_END(v) \
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(((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
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extern void __init c6x_cache_init(void);
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extern void enable_caching(unsigned long start, unsigned long end);
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extern void disable_caching(unsigned long start, unsigned long end);
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extern void L1_cache_off(void);
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extern void L1_cache_on(void);
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extern void L1P_cache_global_invalidate(void);
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extern void L1D_cache_global_invalidate(void);
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extern void L1D_cache_global_writeback(void);
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extern void L1D_cache_global_writeback_invalidate(void);
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extern void L2_cache_set_mode(unsigned int mode);
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extern void L2_cache_global_writeback_invalidate(void);
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extern void L2_cache_global_writeback(void);
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extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L1D_cache_block_writeback_invalidate(unsigned int start,
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unsigned int end);
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extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
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extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
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extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
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extern void L2_cache_block_writeback_invalidate(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_invalidate_nowait(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_writeback_nowait(unsigned int start,
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unsigned int end);
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extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
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unsigned int end);
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#endif /* _ASM_C6X_CACHE_H */
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/*
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* Port on Texas Instruments TMS320C6x architecture
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*
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* Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
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* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_C6X_CACHEFLUSH_H
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#define _ASM_C6X_CACHEFLUSH_H
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#include <linux/spinlock.h>
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#include <asm/setup.h>
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#include <asm/cache.h>
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#include <asm/mman.h>
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#include <asm/page.h>
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#include <asm/string.h>
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/*
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* virtually-indexed cache management (our cache is physically indexed)
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*/
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#define flush_cache_all() do {} while (0)
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#define flush_cache_mm(mm) do {} while (0)
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#define flush_cache_dup_mm(mm) do {} while (0)
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#define flush_cache_range(mm, start, end) do {} while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
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#define flush_cache_vmap(start, end) do {} while (0)
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#define flush_cache_vunmap(start, end) do {} while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do {} while (0)
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#define flush_dcache_mmap_lock(mapping) do {} while (0)
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#define flush_dcache_mmap_unlock(mapping) do {} while (0)
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/*
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* physically-indexed cache management
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*/
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#define flush_icache_range(s, e) \
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do { \
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L1D_cache_block_writeback((s), (e)); \
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L1P_cache_block_invalidate((s), (e)); \
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} while (0)
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#define flush_icache_page(vma, page) \
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do { \
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if ((vma)->vm_flags & PROT_EXEC) \
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L1D_cache_block_writeback_invalidate(page_address(page), \
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(unsigned long) page_address(page) + PAGE_SIZE)); \
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L1P_cache_block_invalidate(page_address(page), \
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(unsigned long) page_address(page) + PAGE_SIZE)); \
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} while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* _ASM_C6X_CACHEFLUSH_H */
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@ -0,0 +1,445 @@
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated
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* Author: Mark Salter <msalter@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <asm/cache.h>
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#include <asm/soc.h>
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/*
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* Internal Memory Control Registers for caches
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*/
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#define IMCR_CCFG 0x0000
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#define IMCR_L1PCFG 0x0020
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#define IMCR_L1PCC 0x0024
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#define IMCR_L1DCFG 0x0040
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#define IMCR_L1DCC 0x0044
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#define IMCR_L2ALLOC0 0x2000
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#define IMCR_L2ALLOC1 0x2004
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#define IMCR_L2ALLOC2 0x2008
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#define IMCR_L2ALLOC3 0x200c
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#define IMCR_L2WBAR 0x4000
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#define IMCR_L2WWC 0x4004
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#define IMCR_L2WIBAR 0x4010
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#define IMCR_L2WIWC 0x4014
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#define IMCR_L2IBAR 0x4018
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#define IMCR_L2IWC 0x401c
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#define IMCR_L1PIBAR 0x4020
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#define IMCR_L1PIWC 0x4024
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#define IMCR_L1DWIBAR 0x4030
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#define IMCR_L1DWIWC 0x4034
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#define IMCR_L1DWBAR 0x4040
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#define IMCR_L1DWWC 0x4044
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#define IMCR_L1DIBAR 0x4048
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#define IMCR_L1DIWC 0x404c
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#define IMCR_L2WB 0x5000
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#define IMCR_L2WBINV 0x5004
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#define IMCR_L2INV 0x5008
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#define IMCR_L1PINV 0x5028
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#define IMCR_L1DWB 0x5040
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#define IMCR_L1DWBINV 0x5044
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#define IMCR_L1DINV 0x5048
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#define IMCR_MAR_BASE 0x8000
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#define IMCR_MAR96_111 0x8180
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#define IMCR_MAR128_191 0x8200
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#define IMCR_MAR224_239 0x8380
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#define IMCR_L2MPFAR 0xa000
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#define IMCR_L2MPFSR 0xa004
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#define IMCR_L2MPFCR 0xa008
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#define IMCR_L2MPLK0 0xa100
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#define IMCR_L2MPLK1 0xa104
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#define IMCR_L2MPLK2 0xa108
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#define IMCR_L2MPLK3 0xa10c
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#define IMCR_L2MPLKCMD 0xa110
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#define IMCR_L2MPLKSTAT 0xa114
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#define IMCR_L2MPPA_BASE 0xa200
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#define IMCR_L1PMPFAR 0xa400
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#define IMCR_L1PMPFSR 0xa404
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#define IMCR_L1PMPFCR 0xa408
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#define IMCR_L1PMPLK0 0xa500
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#define IMCR_L1PMPLK1 0xa504
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#define IMCR_L1PMPLK2 0xa508
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#define IMCR_L1PMPLK3 0xa50c
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#define IMCR_L1PMPLKCMD 0xa510
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#define IMCR_L1PMPLKSTAT 0xa514
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#define IMCR_L1PMPPA_BASE 0xa600
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#define IMCR_L1DMPFAR 0xac00
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#define IMCR_L1DMPFSR 0xac04
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#define IMCR_L1DMPFCR 0xac08
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#define IMCR_L1DMPLK0 0xad00
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#define IMCR_L1DMPLK1 0xad04
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#define IMCR_L1DMPLK2 0xad08
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#define IMCR_L1DMPLK3 0xad0c
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#define IMCR_L1DMPLKCMD 0xad10
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#define IMCR_L1DMPLKSTAT 0xad14
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#define IMCR_L1DMPPA_BASE 0xae00
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#define IMCR_L2PDWAKE0 0xc040
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#define IMCR_L2PDWAKE1 0xc044
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#define IMCR_L2PDSLEEP0 0xc050
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#define IMCR_L2PDSLEEP1 0xc054
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#define IMCR_L2PDSTAT0 0xc060
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#define IMCR_L2PDSTAT1 0xc064
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/*
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* CCFG register values and bits
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*/
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#define L2MODE_0K_CACHE 0x0
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#define L2MODE_32K_CACHE 0x1
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#define L2MODE_64K_CACHE 0x2
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#define L2MODE_128K_CACHE 0x3
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#define L2MODE_256K_CACHE 0x7
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#define L2PRIO_URGENT 0x0
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#define L2PRIO_HIGH 0x1
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#define L2PRIO_MEDIUM 0x2
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#define L2PRIO_LOW 0x3
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#define CCFG_ID 0x100 /* Invalidate L1P bit */
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#define CCFG_IP 0x200 /* Invalidate L1D bit */
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static void __iomem *cache_base;
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/*
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* L1 & L2 caches generic functions
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*/
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#define imcr_get(reg) soc_readl(cache_base + (reg))
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#define imcr_set(reg, value) \
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do { \
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soc_writel((value), cache_base + (reg)); \
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soc_readl(cache_base + (reg)); \
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} while (0)
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static void cache_block_operation_wait(unsigned int wc_reg)
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{
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/* Wait for completion */
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while (imcr_get(wc_reg))
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cpu_relax();
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}
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static DEFINE_SPINLOCK(cache_lock);
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/*
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* Generic function to perform a block cache operation as
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* invalidate or writeback/invalidate
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*/
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static void cache_block_operation(unsigned int *start,
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unsigned int *end,
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unsigned int bar_reg,
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unsigned int wc_reg)
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{
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unsigned long flags;
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unsigned int wcnt =
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(L2_CACHE_ALIGN_CNT((unsigned int) end)
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- L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
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unsigned int wc = 0;
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for (; wcnt; wcnt -= wc, start += wc) {
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loop:
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spin_lock_irqsave(&cache_lock, flags);
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/*
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* If another cache operation is occuring
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*/
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if (unlikely(imcr_get(wc_reg))) {
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Wait for previous operation completion */
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cache_block_operation_wait(wc_reg);
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/* Try again */
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goto loop;
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}
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imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
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if (wcnt > 0xffff)
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wc = 0xffff;
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else
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wc = wcnt;
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/* Set word count value in the WC register */
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imcr_set(wc_reg, wc & 0xffff);
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Wait for completion */
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cache_block_operation_wait(wc_reg);
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}
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}
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static void cache_block_operation_nowait(unsigned int *start,
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unsigned int *end,
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unsigned int bar_reg,
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unsigned int wc_reg)
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{
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unsigned long flags;
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unsigned int wcnt =
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(L2_CACHE_ALIGN_CNT((unsigned int) end)
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- L2_CACHE_ALIGN_LOW((unsigned int) start)) >> 2;
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unsigned int wc = 0;
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for (; wcnt; wcnt -= wc, start += wc) {
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spin_lock_irqsave(&cache_lock, flags);
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imcr_set(bar_reg, L2_CACHE_ALIGN_LOW((unsigned int) start));
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if (wcnt > 0xffff)
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wc = 0xffff;
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else
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wc = wcnt;
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/* Set word count value in the WC register */
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imcr_set(wc_reg, wc & 0xffff);
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spin_unlock_irqrestore(&cache_lock, flags);
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/* Don't wait for completion on last cache operation */
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if (wcnt > 0xffff)
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cache_block_operation_wait(wc_reg);
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}
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}
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/*
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* L1 caches management
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*/
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/*
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* Disable L1 caches
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*/
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void L1_cache_off(void)
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{
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unsigned int dummy;
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imcr_set(IMCR_L1PCFG, 0);
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dummy = imcr_get(IMCR_L1PCFG);
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imcr_set(IMCR_L1DCFG, 0);
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dummy = imcr_get(IMCR_L1DCFG);
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}
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/*
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* Enable L1 caches
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*/
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void L1_cache_on(void)
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{
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unsigned int dummy;
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imcr_set(IMCR_L1PCFG, 7);
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dummy = imcr_get(IMCR_L1PCFG);
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imcr_set(IMCR_L1DCFG, 7);
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dummy = imcr_get(IMCR_L1DCFG);
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}
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/*
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* L1P global-invalidate all
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*/
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void L1P_cache_global_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1PINV, set);
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while (imcr_get(IMCR_L1PINV) & 1)
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cpu_relax();
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}
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/*
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* L1D global-invalidate all
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*
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* Warning: this operation causes all updated data in L1D to
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* be discarded rather than written back to the lower levels of
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* memory
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*/
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void L1D_cache_global_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DINV, set);
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while (imcr_get(IMCR_L1DINV) & 1)
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cpu_relax();
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}
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void L1D_cache_global_writeback(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DWB, set);
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while (imcr_get(IMCR_L1DWB) & 1)
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cpu_relax();
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}
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void L1D_cache_global_writeback_invalidate(void)
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{
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unsigned int set = 1;
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imcr_set(IMCR_L1DWBINV, set);
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while (imcr_get(IMCR_L1DWBINV) & 1)
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cpu_relax();
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}
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/*
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* L2 caches management
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*/
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/*
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* Set L2 operation mode
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*/
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void L2_cache_set_mode(unsigned int mode)
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{
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unsigned int ccfg = imcr_get(IMCR_CCFG);
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/* Clear and set the L2MODE bits in CCFG */
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ccfg &= ~7;
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ccfg |= (mode & 7);
|
||||
imcr_set(IMCR_CCFG, ccfg);
|
||||
ccfg = imcr_get(IMCR_CCFG);
|
||||
}
|
||||
|
||||
/*
|
||||
* L2 global-writeback and global-invalidate all
|
||||
*/
|
||||
void L2_cache_global_writeback_invalidate(void)
|
||||
{
|
||||
imcr_set(IMCR_L2WBINV, 1);
|
||||
while (imcr_get(IMCR_L2WBINV))
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/*
|
||||
* L2 global-writeback all
|
||||
*/
|
||||
void L2_cache_global_writeback(void)
|
||||
{
|
||||
imcr_set(IMCR_L2WB, 1);
|
||||
while (imcr_get(IMCR_L2WB))
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/*
|
||||
* Cacheability controls
|
||||
*/
|
||||
void enable_caching(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
|
||||
unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
|
||||
|
||||
for (; mar <= mar_e; mar += 4)
|
||||
imcr_set(mar, imcr_get(mar) | 1);
|
||||
}
|
||||
|
||||
void disable_caching(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned int mar = IMCR_MAR_BASE + ((start >> 24) << 2);
|
||||
unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2);
|
||||
|
||||
for (; mar <= mar_e; mar += 4)
|
||||
imcr_set(mar, imcr_get(mar) & ~1);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* L1 block operations
|
||||
*/
|
||||
void L1P_cache_block_invalidate(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L1PIBAR, IMCR_L1PIWC);
|
||||
}
|
||||
|
||||
void L1D_cache_block_invalidate(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L1DIBAR, IMCR_L1DIWC);
|
||||
}
|
||||
|
||||
void L1D_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L1DWIBAR, IMCR_L1DWIWC);
|
||||
}
|
||||
|
||||
void L1D_cache_block_writeback(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L1DWBAR, IMCR_L1DWWC);
|
||||
}
|
||||
|
||||
/*
|
||||
* L2 block operations
|
||||
*/
|
||||
void L2_cache_block_invalidate(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2IBAR, IMCR_L2IWC);
|
||||
}
|
||||
|
||||
void L2_cache_block_writeback(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2WBAR, IMCR_L2WWC);
|
||||
}
|
||||
|
||||
void L2_cache_block_writeback_invalidate(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2WIBAR, IMCR_L2WIWC);
|
||||
}
|
||||
|
||||
void L2_cache_block_invalidate_nowait(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation_nowait((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2IBAR, IMCR_L2IWC);
|
||||
}
|
||||
|
||||
void L2_cache_block_writeback_nowait(unsigned int start, unsigned int end)
|
||||
{
|
||||
cache_block_operation_nowait((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2WBAR, IMCR_L2WWC);
|
||||
}
|
||||
|
||||
void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
|
||||
unsigned int end)
|
||||
{
|
||||
cache_block_operation_nowait((unsigned int *) start,
|
||||
(unsigned int *) end,
|
||||
IMCR_L2WIBAR, IMCR_L2WIWC);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* L1 and L2 caches configuration
|
||||
*/
|
||||
void __init c6x_cache_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "ti,c64x+cache");
|
||||
if (!node)
|
||||
return;
|
||||
|
||||
cache_base = of_iomap(node, 0);
|
||||
|
||||
of_node_put(node);
|
||||
|
||||
if (!cache_base)
|
||||
return;
|
||||
|
||||
/* Set L2 caches on the the whole L2 SRAM memory */
|
||||
L2_cache_set_mode(L2MODE_SIZE);
|
||||
|
||||
/* Enable L1 */
|
||||
L1_cache_on();
|
||||
}
|
||||
Loading…
Reference in New Issue