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ARM: tegra30: clk: Fix output_rate overflow 

Change the type of variable from "unsigned long" to "u64".
This avoids the overflow while clock rate calculating.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
hifive-unleashed-5.1
Mark Zhang 2012-10-16 16:31:49 +08:00 committed by Stephen Warren
parent ddffeb8c4d
commit 786621308c
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-tegra/tegra30_clocks.c
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@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_tegra *c = to_clk_tegra(hw);
unsigned long input_rate = *prate;
unsigned long output_rate = *prate;
u64 output_rate = *prate;
const struct clk_pll_freq_table *sel;
struct clk_pll_freq_table cfg;
int mul;