staging: et131x: Remove duplicate code for fbr[0, 1]
Several places in et131x.c code is duplicated for fbr[0] and fbr[1]. Remove the duplicate lines and use loops to run over both indicies. Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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c4ff7ef5cf
commit
788ca84ac7
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@ -176,8 +176,8 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere S
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#define PARM_DMA_CACHE_DEF 0
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/* RX defines */
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#define FBR_CHUNKS 32
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#define MAX_DESC_PER_RING_RX 1024
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#define FBR_CHUNKS 32
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#define MAX_DESC_PER_RING_RX 1024
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/* number of RFDs - default and min */
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#define RFD_LOW_WATER_MARK 40
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@ -1847,6 +1847,7 @@ static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
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u32 entry;
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u32 psr_num_des;
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unsigned long flags;
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u8 id;
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/* Halt RXDMA to perform the reconfigure. */
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et131x_rx_dma_disable(adapter);
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@ -1874,57 +1875,53 @@ static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
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/* These local variables track the PSR in the adapter structure */
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rx_local->local_psr_full = 0;
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/* Now's the best time to initialize FBR1 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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for (id = 0; id < NUM_FBRS; id++) {
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u32 *num_des;
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u32 *full_offset;
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u32 *min_des;
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u32 *base_hi;
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u32 *base_lo;
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if (id == 0) {
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num_des = &rx_dma->fbr1_num_des;
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full_offset = &rx_dma->fbr1_full_offset;
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min_des = &rx_dma->fbr1_min_des;
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base_hi = &rx_dma->fbr1_base_hi;
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base_lo = &rx_dma->fbr1_base_lo;
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} else {
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num_des = &rx_dma->fbr0_num_des;
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full_offset = &rx_dma->fbr0_full_offset;
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min_des = &rx_dma->fbr0_min_des;
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base_hi = &rx_dma->fbr0_base_hi;
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base_lo = &rx_dma->fbr0_base_lo;
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}
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/* Now's the best time to initialize FBR contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[id]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[id]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[id]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[id]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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/* Set the address and parameters of Free buffer ring 1 and 0
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* into the 1310's registers
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*/
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writel(upper_32_bits(rx_local->fbr[id]->ring_physaddr), base_hi);
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writel(lower_32_bits(rx_local->fbr[id]->ring_physaddr), base_lo);
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writel(rx_local->fbr[id]->num_entries - 1, num_des);
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writel(ET_DMA10_WRAP, full_offset);
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/* This variable tracks the free buffer ring 1 full position,
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* so it has to match the above.
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*/
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rx_local->fbr[id]->local_full = ET_DMA10_WRAP;
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writel(((rx_local->fbr[id]->num_entries *
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LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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min_des);
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}
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/* Set the address and parameters of Free buffer ring 1 (and 0 if
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* required) into the 1310's registers
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*/
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writel(upper_32_bits(rx_local->fbr[0]->ring_physaddr),
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&rx_dma->fbr1_base_hi);
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writel(lower_32_bits(rx_local->fbr[0]->ring_physaddr),
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&rx_dma->fbr1_base_lo);
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writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
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/* This variable tracks the free buffer ring 1 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr1_min_des);
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/* Now's the best time to initialize FBR0 contents */
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fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
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for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
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fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
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fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
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fbr_entry->word2 = entry;
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fbr_entry++;
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}
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writel(upper_32_bits(rx_local->fbr[1]->ring_physaddr),
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&rx_dma->fbr0_base_hi);
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writel(lower_32_bits(rx_local->fbr[1]->ring_physaddr),
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&rx_dma->fbr0_base_lo);
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writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
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writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
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/* This variable tracks the free buffer ring 0 full position, so it
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* has to match the above.
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*/
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rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
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writel(
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((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
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&rx_dma->fbr0_min_des);
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/* Program the number of packets we will receive before generating an
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* interrupt.
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* For version B silicon, this value gets updated once autoneg is
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@ -2258,7 +2255,8 @@ static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
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* @mask: correct mask
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*/
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static void et131x_align_allocated_memory(struct et131x_adapter *adapter,
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dma_addr_t *phys_addr, dma_addr_t *offset,
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dma_addr_t *phys_addr,
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dma_addr_t *offset,
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u64 mask)
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{
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u64 new_addr = *phys_addr & ~mask;
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@ -2286,6 +2284,7 @@ static void et131x_align_allocated_memory(struct et131x_adapter *adapter,
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*/
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static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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{
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u8 id;
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u32 i, j;
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u32 bufsize;
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u32 pktstat_ringsize, fbr_chunksize;
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@ -2337,158 +2336,95 @@ static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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adapter->rx_ring.fbr[1]->num_entries +
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adapter->rx_ring.fbr[0]->num_entries;
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/* Allocate an area of memory for Free Buffer Ring 1 */
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bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) +
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0xfff;
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rx_ring->fbr[0]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
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for (id = 0; id < NUM_FBRS; id++) {
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/* Allocate an area of memory for Free Buffer Ring */
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bufsize = (sizeof(struct fbr_desc) *
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rx_ring->fbr[id]->num_entries) + 0xfff;
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rx_ring->fbr[id]->ring_virtaddr =
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dma_alloc_coherent(&adapter->pdev->dev,
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bufsize,
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&rx_ring->fbr[0]->ring_physaddr,
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&rx_ring->fbr[id]->ring_physaddr,
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GFP_KERNEL);
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if (!rx_ring->fbr[0]->ring_virtaddr) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Free Buffer Ring 1\n");
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return -ENOMEM;
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}
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/* Align Free Buffer Ring 1 on a 4K boundary */
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et131x_align_allocated_memory(adapter,
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&rx_ring->fbr[0]->ring_physaddr,
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&rx_ring->fbr[0]->offset, 0x0FFF);
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rx_ring->fbr[0]->ring_virtaddr =
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(void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
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rx_ring->fbr[0]->offset);
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/* Allocate an area of memory for Free Buffer Ring 0 */
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bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) +
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0xfff;
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rx_ring->fbr[1]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
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bufsize,
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&rx_ring->fbr[1]->ring_physaddr,
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GFP_KERNEL);
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if (!rx_ring->fbr[1]->ring_virtaddr) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Free Buffer Ring 0\n");
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return -ENOMEM;
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}
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/* Align Free Buffer Ring 0 on a 4K boundary */
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et131x_align_allocated_memory(adapter,
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&rx_ring->fbr[1]->ring_physaddr,
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&rx_ring->fbr[1]->offset, 0x0FFF);
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rx_ring->fbr[1]->ring_virtaddr =
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(void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
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rx_ring->fbr[1]->offset);
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for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
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dma_addr_t fbr1_tmp_physaddr;
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dma_addr_t fbr1_offset;
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u32 fbr1_align;
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/* This code allocates an area of memory big enough for N
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* free buffers + (buffer_size - 1) so that the buffers can
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* be aligned on 4k boundaries. If each buffer were aligned
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* to a buffer_size boundary, the effect would be to double
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* the size of FBR0. By allocating N buffers at once, we
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* reduce this overhead.
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*/
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if (rx_ring->fbr[0]->buffsize > 4096)
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fbr1_align = 4096;
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else
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fbr1_align = rx_ring->fbr[0]->buffsize;
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fbr_chunksize =
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(FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
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rx_ring->fbr[0]->mem_virtaddrs[i] =
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dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
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&rx_ring->fbr[0]->mem_physaddrs[i],
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GFP_KERNEL);
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if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
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if (!rx_ring->fbr[id]->ring_virtaddr) {
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dev_err(&adapter->pdev->dev,
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"Could not alloc memory\n");
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"Cannot alloc memory for Free Buffer Ring %d\n", id);
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return -ENOMEM;
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}
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/* See NOTE in "Save Physical Address" comment above */
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fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
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/* Align Free Buffer Ring on a 4K boundary */
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et131x_align_allocated_memory(adapter,
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&fbr1_tmp_physaddr,
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&fbr1_offset, (fbr1_align - 1));
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&rx_ring->fbr[id]->ring_physaddr,
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&rx_ring->fbr[id]->offset, 0x0FFF);
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for (j = 0; j < FBR_CHUNKS; j++) {
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u32 index = (i * FBR_CHUNKS) + j;
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/* Save the Virtual address of this index for quick
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* access later
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*/
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rx_ring->fbr[0]->virt[index] =
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(u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
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(j * rx_ring->fbr[0]->buffsize) + fbr1_offset;
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/* now store the physical address in the descriptor
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* so the device can access it
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*/
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rx_ring->fbr[0]->bus_high[index] =
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upper_32_bits(fbr1_tmp_physaddr);
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rx_ring->fbr[0]->bus_low[index] =
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lower_32_bits(fbr1_tmp_physaddr);
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fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize;
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rx_ring->fbr[0]->buffer1[index] =
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rx_ring->fbr[0]->virt[index];
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rx_ring->fbr[0]->buffer2[index] =
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rx_ring->fbr[0]->virt[index] - 4;
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}
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rx_ring->fbr[id]->ring_virtaddr =
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(void *)((u8 *) rx_ring->fbr[id]->ring_virtaddr +
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rx_ring->fbr[id]->offset);
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}
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/* Same for FBR0 (if in use) */
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for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
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dma_addr_t fbr0_tmp_physaddr;
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dma_addr_t fbr0_offset;
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for (id = 0; id < NUM_FBRS; id++) {
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for (i = 0; i < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS); i++) {
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dma_addr_t fbr_tmp_physaddr;
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dma_addr_t fbr_offset;
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u32 fbr_align;
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fbr_chunksize =
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((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
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rx_ring->fbr[1]->mem_virtaddrs[i] =
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dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
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&rx_ring->fbr[1]->mem_physaddrs[i],
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GFP_KERNEL);
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/* This code allocates an area of memory big enough for
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* N free buffers + (buffer_size - 1) so that the
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* buffers can be aligned on 4k boundaries. If each
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* buffer were aligned to a buffer_size boundary, the
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* effect would be to double the size of FBR0. By
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* allocating N buffers at once, we reduce this overhead
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*/
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if (id == 0 && rx_ring->fbr[id]->buffsize > 4096)
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fbr_align = 4096;
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else
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fbr_align = rx_ring->fbr[id]->buffsize;
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if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
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dev_err(&adapter->pdev->dev,
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"Could not alloc memory\n");
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return -ENOMEM;
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}
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fbr_chunksize = (FBR_CHUNKS *
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rx_ring->fbr[id]->buffsize) + fbr_align - 1;
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rx_ring->fbr[id]->mem_virtaddrs[i] = dma_alloc_coherent(
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&adapter->pdev->dev, fbr_chunksize,
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&rx_ring->fbr[id]->mem_physaddrs[i],
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GFP_KERNEL);
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/* See NOTE in "Save Physical Address" comment above */
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fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
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if (!rx_ring->fbr[id]->mem_virtaddrs[i]) {
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dev_err(&adapter->pdev->dev,
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"Could not alloc memory\n");
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return -ENOMEM;
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}
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et131x_align_allocated_memory(adapter,
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&fbr0_tmp_physaddr,
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&fbr0_offset,
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rx_ring->fbr[1]->buffsize - 1);
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/* See NOTE in "Save Physical Address" comment above */
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fbr_tmp_physaddr = rx_ring->fbr[id]->mem_physaddrs[i];
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for (j = 0; j < FBR_CHUNKS; j++) {
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u32 index = (i * FBR_CHUNKS) + j;
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et131x_align_allocated_memory(adapter,
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&fbr_tmp_physaddr,
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&fbr_offset,
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(fbr_align - 1));
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rx_ring->fbr[1]->virt[index] =
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(u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
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(j * rx_ring->fbr[1]->buffsize) + fbr0_offset;
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for (j = 0; j < FBR_CHUNKS; j++) {
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u32 index = (i * FBR_CHUNKS) + j;
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rx_ring->fbr[1]->bus_high[index] =
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upper_32_bits(fbr0_tmp_physaddr);
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rx_ring->fbr[1]->bus_low[index] =
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lower_32_bits(fbr0_tmp_physaddr);
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/* Save the Virtual address of this index for
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* quick access later
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*/
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rx_ring->fbr[id]->virt[index] =
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(u8 *) rx_ring->fbr[id]->mem_virtaddrs[i] +
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(j * rx_ring->fbr[id]->buffsize) + fbr_offset;
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fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize;
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/* now store the physical address in the
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* descriptor so the device can access it
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*/
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rx_ring->fbr[id]->bus_high[index] =
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upper_32_bits(fbr_tmp_physaddr);
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rx_ring->fbr[id]->bus_low[index] =
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lower_32_bits(fbr_tmp_physaddr);
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rx_ring->fbr[1]->buffer1[index] =
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rx_ring->fbr[1]->virt[index];
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rx_ring->fbr[1]->buffer2[index] =
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rx_ring->fbr[1]->virt[index] - 4;
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fbr_tmp_physaddr += rx_ring->fbr[id]->buffsize;
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rx_ring->fbr[id]->buffer1[index] =
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rx_ring->fbr[id]->virt[index];
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rx_ring->fbr[id]->buffer2[index] =
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rx_ring->fbr[id]->virt[index] - 4;
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}
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}
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}
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@ -2557,6 +2493,7 @@ static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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*/
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static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
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{
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u8 id;
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u32 index;
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u32 bufsize;
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u32 pktstat_ringsize;
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@ -2578,80 +2515,48 @@ static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
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kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
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}
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/* Free Free Buffer Ring 1 */
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if (rx_ring->fbr[0]->ring_virtaddr) {
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/* First the packet memory */
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for (index = 0; index <
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(rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
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||||
if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
|
||||
u32 fbr1_align;
|
||||
/* Free Free Buffer Rings */
|
||||
for (id = 0; id < NUM_FBRS; id++) {
|
||||
if (rx_ring->fbr[id]->ring_virtaddr) {
|
||||
/* First the packet memory */
|
||||
for (index = 0; index <
|
||||
(rx_ring->fbr[id]->num_entries / FBR_CHUNKS);
|
||||
index++) {
|
||||
if (rx_ring->fbr[id]->mem_virtaddrs[index]) {
|
||||
u32 fbr_align;
|
||||
|
||||
if (rx_ring->fbr[0]->buffsize > 4096)
|
||||
fbr1_align = 4096;
|
||||
else
|
||||
fbr1_align = rx_ring->fbr[0]->buffsize;
|
||||
if (rx_ring->fbr[id]->buffsize > 4096)
|
||||
fbr_align = 4096;
|
||||
else
|
||||
fbr_align = rx_ring->fbr[id]->buffsize;
|
||||
|
||||
bufsize =
|
||||
(rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
|
||||
fbr1_align - 1;
|
||||
bufsize =
|
||||
(rx_ring->fbr[id]->buffsize * FBR_CHUNKS) +
|
||||
fbr_align - 1;
|
||||
|
||||
dma_free_coherent(&adapter->pdev->dev,
|
||||
bufsize,
|
||||
rx_ring->fbr[0]->mem_virtaddrs[index],
|
||||
rx_ring->fbr[0]->mem_physaddrs[index]);
|
||||
dma_free_coherent(&adapter->pdev->dev,
|
||||
bufsize,
|
||||
rx_ring->fbr[id]->mem_virtaddrs[index],
|
||||
rx_ring->fbr[id]->mem_physaddrs[index]);
|
||||
|
||||
rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
|
||||
rx_ring->fbr[id]->mem_virtaddrs[index] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now the FIFO itself */
|
||||
rx_ring->fbr[id]->ring_virtaddr = (void *)((u8 *)
|
||||
rx_ring->fbr[id]->ring_virtaddr - rx_ring->fbr[id]->offset);
|
||||
|
||||
bufsize =
|
||||
(sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries) +
|
||||
0xfff;
|
||||
|
||||
dma_free_coherent(&adapter->pdev->dev, bufsize,
|
||||
rx_ring->fbr[id]->ring_virtaddr,
|
||||
rx_ring->fbr[id]->ring_physaddr);
|
||||
|
||||
rx_ring->fbr[id]->ring_virtaddr = NULL;
|
||||
}
|
||||
|
||||
/* Now the FIFO itself */
|
||||
rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
|
||||
rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
|
||||
|
||||
bufsize =
|
||||
(sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) +
|
||||
0xfff;
|
||||
|
||||
dma_free_coherent(&adapter->pdev->dev, bufsize,
|
||||
rx_ring->fbr[0]->ring_virtaddr,
|
||||
rx_ring->fbr[0]->ring_physaddr);
|
||||
|
||||
rx_ring->fbr[0]->ring_virtaddr = NULL;
|
||||
}
|
||||
|
||||
/* Now the same for Free Buffer Ring 0 */
|
||||
if (rx_ring->fbr[1]->ring_virtaddr) {
|
||||
/* First the packet memory */
|
||||
for (index = 0; index <
|
||||
(rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
|
||||
if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
|
||||
bufsize =
|
||||
(rx_ring->fbr[1]->buffsize *
|
||||
(FBR_CHUNKS + 1)) - 1;
|
||||
|
||||
dma_free_coherent(&adapter->pdev->dev,
|
||||
bufsize,
|
||||
rx_ring->fbr[1]->mem_virtaddrs[index],
|
||||
rx_ring->fbr[1]->mem_physaddrs[index]);
|
||||
|
||||
rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now the FIFO itself */
|
||||
rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
|
||||
rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
|
||||
|
||||
bufsize =
|
||||
(sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) +
|
||||
0xfff;
|
||||
|
||||
dma_free_coherent(&adapter->pdev->dev,
|
||||
bufsize,
|
||||
rx_ring->fbr[1]->ring_virtaddr,
|
||||
rx_ring->fbr[1]->ring_physaddr);
|
||||
|
||||
rx_ring->fbr[1]->ring_virtaddr = NULL;
|
||||
}
|
||||
|
||||
/* Free Packet Status Ring */
|
||||
|
@ -2780,43 +2685,36 @@ static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
|
|||
if (
|
||||
(ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) ||
|
||||
(ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) {
|
||||
u32 *offset;
|
||||
u8 id;
|
||||
struct fbr_desc *next;
|
||||
|
||||
spin_lock_irqsave(&adapter->fbr_lock, flags);
|
||||
|
||||
if (ring_index == 1) {
|
||||
struct fbr_desc *next = (struct fbr_desc *)
|
||||
(rx_local->fbr[0]->ring_virtaddr) +
|
||||
INDEX10(rx_local->fbr[0]->local_full);
|
||||
|
||||
/* Handle the Free Buffer Ring advancement here. Write
|
||||
* the PA / Buffer Index for the returned buffer into
|
||||
* the oldest (next to be freed)FBR entry
|
||||
*/
|
||||
next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
|
||||
next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
|
||||
next->word2 = buff_index;
|
||||
|
||||
writel(bump_free_buff_ring(
|
||||
&rx_local->fbr[0]->local_full,
|
||||
rx_local->fbr[0]->num_entries - 1),
|
||||
&rx_dma->fbr1_full_offset);
|
||||
id = 0;
|
||||
offset = &rx_dma->fbr1_full_offset;
|
||||
} else {
|
||||
struct fbr_desc *next = (struct fbr_desc *)
|
||||
rx_local->fbr[1]->ring_virtaddr +
|
||||
INDEX10(rx_local->fbr[1]->local_full);
|
||||
|
||||
/* Handle the Free Buffer Ring advancement here. Write
|
||||
* the PA / Buffer Index for the returned buffer into
|
||||
* the oldest (next to be freed) FBR entry
|
||||
*/
|
||||
next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
|
||||
next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
|
||||
next->word2 = buff_index;
|
||||
|
||||
writel(bump_free_buff_ring(
|
||||
&rx_local->fbr[1]->local_full,
|
||||
rx_local->fbr[1]->num_entries - 1),
|
||||
&rx_dma->fbr0_full_offset);
|
||||
id = 1;
|
||||
offset = &rx_dma->fbr0_full_offset;
|
||||
}
|
||||
|
||||
next = (struct fbr_desc *) (rx_local->fbr[id]->ring_virtaddr) +
|
||||
INDEX10(rx_local->fbr[id]->local_full);
|
||||
|
||||
/* Handle the Free Buffer Ring advancement here. Write
|
||||
* the PA / Buffer Index for the returned buffer into
|
||||
* the oldest (next to be freed)FBR entry
|
||||
*/
|
||||
next->addr_hi = rx_local->fbr[id]->bus_high[buff_index];
|
||||
next->addr_lo = rx_local->fbr[id]->bus_low[buff_index];
|
||||
next->word2 = buff_index;
|
||||
|
||||
writel(bump_free_buff_ring(
|
||||
&rx_local->fbr[id]->local_full,
|
||||
rx_local->fbr[id]->num_entries - 1),
|
||||
offset);
|
||||
|
||||
spin_unlock_irqrestore(&adapter->fbr_lock, flags);
|
||||
} else {
|
||||
dev_err(&adapter->pdev->dev,
|
||||
|
|
Loading…
Reference in a new issue