Merge branch 'sh/intc-extension'
Paul Mundt
commit
7896cd0f5a
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@ -259,6 +259,43 @@ static void intc_disable(unsigned int irq)
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}
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}
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static void (*intc_enable_noprio_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_field,
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[MODE_MASK_REG] = intc_mode_zero,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_field,
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[MODE_PCLR_REG] = intc_mode_field,
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};
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static void intc_enable_disable(struct intc_desc_int *d,
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unsigned long handle, int do_enable)
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{
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unsigned long addr;
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unsigned int cpu;
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void (*fn)(unsigned long, unsigned long,
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void (*)(unsigned long, unsigned long, unsigned long),
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unsigned int);
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if (do_enable) {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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} else {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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fn = intc_disable_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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}
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}
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static int intc_set_wake(unsigned int irq, unsigned int on)
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{
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return 0; /* allow wakeup, but setup hardware in intc_suspend() */
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@ -400,11 +437,11 @@ static unsigned int __init intc_get_reg(struct intc_desc_int *d,
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static intc_enum __init intc_grp_id(struct intc_desc *desc,
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intc_enum enum_id)
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{
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struct intc_group *g = desc->groups;
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struct intc_group *g = desc->hw.groups;
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unsigned int i, j;
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for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
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g = desc->groups + i;
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for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
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g = desc->hw.groups + i;
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for (j = 0; g->enum_ids[j]; j++) {
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if (g->enum_ids[j] != enum_id)
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@ -417,19 +454,21 @@ static intc_enum __init intc_grp_id(struct intc_desc *desc,
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return 0;
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}
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static unsigned int __init intc_mask_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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static unsigned int __init _intc_mask_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int *reg_idx,
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unsigned int *fld_idx)
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{
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struct intc_mask_reg *mr = desc->mask_regs;
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unsigned int i, j, fn, mode;
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struct intc_mask_reg *mr = desc->hw.mask_regs;
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unsigned int fn, mode;
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unsigned long reg_e, reg_d;
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for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
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mr = desc->mask_regs + i;
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while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
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mr = desc->hw.mask_regs + *reg_idx;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
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if (mr->enum_ids[*fld_idx] != enum_id)
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continue;
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if (mr->set_reg && mr->clr_reg) {
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@ -455,29 +494,49 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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1,
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(mr->reg_width - 1) - j);
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(mr->reg_width - 1) - *fld_idx);
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}
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*fld_idx = 0;
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(*reg_idx)++;
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}
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return 0;
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}
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static unsigned int __init intc_mask_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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unsigned int i = 0;
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unsigned int j = 0;
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unsigned int ret;
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ret = _intc_mask_data(desc, d, enum_id, &i, &j);
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if (ret)
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return ret;
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if (do_grps)
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return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static unsigned int __init intc_prio_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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static unsigned int __init _intc_prio_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int *reg_idx,
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unsigned int *fld_idx)
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{
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struct intc_prio_reg *pr = desc->prio_regs;
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unsigned int i, j, fn, mode, bit;
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struct intc_prio_reg *pr = desc->hw.prio_regs;
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unsigned int fn, n, mode, bit;
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unsigned long reg_e, reg_d;
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for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
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pr = desc->prio_regs + i;
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while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
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pr = desc->hw.prio_regs + *reg_idx;
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for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
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if (pr->enum_ids[j] != enum_id)
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for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
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if (pr->enum_ids[*fld_idx] != enum_id)
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continue;
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if (pr->set_reg && pr->clr_reg) {
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@ -495,34 +554,79 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
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}
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fn += (pr->reg_width >> 3) - 1;
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n = *fld_idx + 1;
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BUG_ON((j + 1) * pr->field_width > pr->reg_width);
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BUG_ON(n * pr->field_width > pr->reg_width);
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bit = pr->reg_width - ((j + 1) * pr->field_width);
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bit = pr->reg_width - (n * pr->field_width);
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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pr->field_width, bit);
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}
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*fld_idx = 0;
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(*reg_idx)++;
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}
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return 0;
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}
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static unsigned int __init intc_prio_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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unsigned int i = 0;
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unsigned int j = 0;
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unsigned int ret;
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ret = _intc_prio_data(desc, d, enum_id, &i, &j);
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if (ret)
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return ret;
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if (do_grps)
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return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static void __init intc_enable_disable_enum(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int enable)
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{
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unsigned int i, j, data;
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/* go through and enable/disable all mask bits */
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i = j = 0;
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do {
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data = _intc_mask_data(desc, d, enum_id, &i, &j);
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if (data)
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intc_enable_disable(d, data, enable);
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j++;
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} while (data);
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/* go through and enable/disable all priority fields */
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i = j = 0;
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do {
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data = _intc_prio_data(desc, d, enum_id, &i, &j);
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if (data)
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intc_enable_disable(d, data, enable);
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j++;
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} while (data);
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}
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static unsigned int __init intc_ack_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id)
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{
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struct intc_mask_reg *mr = desc->ack_regs;
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struct intc_mask_reg *mr = desc->hw.ack_regs;
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unsigned int i, j, fn, mode;
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unsigned long reg_e, reg_d;
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for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
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mr = desc->ack_regs + i;
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for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
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mr = desc->hw.ack_regs + i;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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@ -549,11 +653,11 @@ static unsigned int __init intc_sense_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id)
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{
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struct intc_sense_reg *sr = desc->sense_regs;
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struct intc_sense_reg *sr = desc->hw.sense_regs;
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unsigned int i, j, fn, bit;
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for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
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sr = desc->sense_regs + i;
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for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
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sr = desc->hw.sense_regs + i;
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for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
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if (sr->enum_ids[j] != enum_id)
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@ -656,7 +760,7 @@ static void __init intc_register_irq(struct intc_desc *desc,
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/* irq should be disabled by default */
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d->chip.mask(irq);
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if (desc->ack_regs)
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if (desc->hw.ack_regs)
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ack_handle[irq] = intc_ack_data(desc, d, enum_id);
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}
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@ -684,6 +788,7 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
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void __init register_intc_controller(struct intc_desc *desc)
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{
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unsigned int i, k, smp;
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struct intc_hw_desc *hw = &desc->hw;
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struct intc_desc_int *d;
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d = kzalloc(sizeof(*d), GFP_NOWAIT);
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@ -691,10 +796,10 @@ void __init register_intc_controller(struct intc_desc *desc)
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INIT_LIST_HEAD(&d->list);
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list_add(&d->list, &intc_list);
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d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
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d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
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d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
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d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
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d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
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d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
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d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
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d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
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d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
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#ifdef CONFIG_SMP
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@ -702,30 +807,31 @@ void __init register_intc_controller(struct intc_desc *desc)
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#endif
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k = 0;
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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smp = IS_SMP(desc->mask_regs[i]);
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k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
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k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
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if (hw->mask_regs) {
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for (i = 0; i < hw->nr_mask_regs; i++) {
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smp = IS_SMP(hw->mask_regs[i]);
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k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
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k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
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}
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}
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if (desc->prio_regs) {
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d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
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if (hw->prio_regs) {
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d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
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GFP_NOWAIT);
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for (i = 0; i < desc->nr_prio_regs; i++) {
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smp = IS_SMP(desc->prio_regs[i]);
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k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
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k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
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for (i = 0; i < hw->nr_prio_regs; i++) {
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smp = IS_SMP(hw->prio_regs[i]);
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k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
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k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
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}
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}
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if (desc->sense_regs) {
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d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
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if (hw->sense_regs) {
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d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
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GFP_NOWAIT);
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for (i = 0; i < desc->nr_sense_regs; i++) {
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k += save_reg(d, k, desc->sense_regs[i].reg, 0);
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}
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for (i = 0; i < hw->nr_sense_regs; i++)
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k += save_reg(d, k, hw->sense_regs[i].reg, 0);
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}
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d->chip.name = desc->name;
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@ -738,18 +844,23 @@ void __init register_intc_controller(struct intc_desc *desc)
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d->chip.set_type = intc_set_sense;
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d->chip.set_wake = intc_set_wake;
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if (desc->ack_regs) {
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for (i = 0; i < desc->nr_ack_regs; i++)
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k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
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if (hw->ack_regs) {
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for (i = 0; i < hw->nr_ack_regs; i++)
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k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
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d->chip.mask_ack = intc_mask_ack;
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}
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/* disable bits matching force_enable before registering irqs */
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if (desc->force_enable)
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intc_enable_disable_enum(desc, d, desc->force_enable, 0);
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BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
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/* register the vectors one by one */
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for (i = 0; i < desc->nr_vectors; i++) {
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struct intc_vect *vect = desc->vectors + i;
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for (i = 0; i < hw->nr_vectors; i++) {
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struct intc_vect *vect = hw->vectors + i;
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unsigned int irq = evt2irq(vect->vect);
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struct irq_desc *irq_desc;
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@ -764,8 +875,8 @@ void __init register_intc_controller(struct intc_desc *desc)
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intc_register_irq(desc, d, vect->enum_id, irq);
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for (k = i + 1; k < desc->nr_vectors; k++) {
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struct intc_vect *vect2 = desc->vectors + k;
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for (k = i + 1; k < hw->nr_vectors; k++) {
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struct intc_vect *vect2 = hw->vectors + k;
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unsigned int irq2 = evt2irq(vect2->vect);
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if (vect->enum_id != vect2->enum_id)
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@ -790,6 +901,10 @@ void __init register_intc_controller(struct intc_desc *desc)
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set_irq_data(irq2, (void *)irq);
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}
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}
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/* enable bits matching force_enable after registering irqs */
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if (desc->force_enable)
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intc_enable_disable_enum(desc, d, desc->force_enable, 1);
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}
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static int intc_suspend(struct sys_device *dev, pm_message_t state)
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@ -45,7 +45,7 @@ struct intc_sense_reg {
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#define INTC_SMP(stride, nr)
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#endif
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struct intc_desc {
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struct intc_hw_desc {
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struct intc_vect *vectors;
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unsigned int nr_vectors;
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struct intc_group *groups;
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@ -56,29 +56,39 @@ struct intc_desc {
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unsigned int nr_prio_regs;
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struct intc_sense_reg *sense_regs;
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unsigned int nr_sense_regs;
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char *name;
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struct intc_mask_reg *ack_regs;
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unsigned int nr_ack_regs;
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};
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#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
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#define INTC_HW_DESC(vectors, groups, mask_regs, \
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prio_regs, sense_regs, ack_regs) \
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{ \
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_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
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_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
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_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
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}
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struct intc_desc {
|
||||
char *name;
|
||||
intc_enum force_enable;
|
||||
struct intc_hw_desc hw;
|
||||
};
|
||||
|
||||
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
|
||||
mask_regs, prio_regs, sense_regs) \
|
||||
struct intc_desc symbol __initdata = { \
|
||||
_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
|
||||
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
|
||||
_INTC_ARRAY(sense_regs), \
|
||||
chipname, \
|
||||
.name = chipname, \
|
||||
.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
|
||||
prio_regs, sense_regs, NULL), \
|
||||
}
|
||||
|
||||
#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
|
||||
mask_regs, prio_regs, sense_regs, ack_regs) \
|
||||
struct intc_desc symbol __initdata = { \
|
||||
_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
|
||||
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
|
||||
_INTC_ARRAY(sense_regs), \
|
||||
chipname, \
|
||||
_INTC_ARRAY(ack_regs), \
|
||||
.name = chipname, \
|
||||
.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
|
||||
prio_regs, sense_regs, ack_regs), \
|
||||
}
|
||||
|
||||
void __init register_intc_controller(struct intc_desc *desc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue