ARM: tegra: Add firmware calls required for suspend-resume on Tegra30
In order to suspend-resume CPU with Trusted Foundations firmware being present on Tegra30, the LP1/LP2 boot vectors and CPU caches need to be set up using the firmware calls and then suspend code shall avoid re-disabling parts that were disabled by the firmware. Tested-by: Robert Yang <decatf@gmail.com> Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.2
Dmitry Osipenko
Thierry Reding
parent
dae84be59d
commit
78ee399f16
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@ -33,11 +33,13 @@
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#include <soc/tegra/pmc.h>
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#include <asm/cacheflush.h>
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#include <asm/firmware.h>
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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#include <asm/trusted_foundations.h>
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#include "iomap.h"
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#include "pm.h"
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@ -159,6 +161,28 @@ int tegra_cpu_do_idle(void)
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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/*
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* L2 cache disabling using kernel API only allowed when all
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* secondary CPU's are offline. Cache have to be disabled with
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* MMU-on if cache maintenance is done via Trusted Foundations
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* firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
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* if any of secondary CPU's is online and this is the LP2-idle
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* code-path only for Tegra20/30.
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*/
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if (trusted_foundations_registered())
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outer_disable();
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/*
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* Note that besides of setting up CPU reset vector this firmware
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* call may also do the following, depending on the FW version:
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* 1) Disable L2. But this doesn't matter since we already
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* disabled the L2.
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* 2) Disable D-cache. This need to be taken into account in
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* particular by the tegra_disable_clean_inv_dcache() which
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* shall avoid the re-disable.
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*/
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call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
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setup_mm_for_reboot();
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tegra_sleep_cpu_finish(v2p);
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@ -197,6 +221,14 @@ void tegra_idle_lp2_last(void)
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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/*
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* Resume L2 cache if it wasn't re-enabled early during resume,
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* which is the case for Tegra30 that has to re-enable the cache
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* via firmware call. In other cases cache is already enabled and
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* hence re-enabling is a no-op. This is always a no-op on Tegra114+.
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*/
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outer_resume();
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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}
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@ -215,6 +247,15 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
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static int tegra_sleep_core(unsigned long v2p)
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{
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/*
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* Cache have to be disabled with MMU-on if cache maintenance is done
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* via Trusted Foundations firmware. This is a no-op on Tegra114+.
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*/
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if (trusted_foundations_registered())
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outer_disable();
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call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
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setup_mm_for_reboot();
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tegra_sleep_core_finish(v2p);
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@ -342,6 +383,14 @@ static int tegra_suspend_enter(suspend_state_t state)
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
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/*
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* Resume L2 cache if it wasn't re-enabled early during resume,
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* which is the case for Tegra30 that has to re-enable the cache
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* via firmware call. In other cases cache is already enabled and
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* hence re-enabling is a no-op.
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*/
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outer_resume();
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switch (mode) {
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case TEGRA_SUSPEND_LP1:
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tegra_suspend_exit_lp1();
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@ -20,6 +20,7 @@
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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@ -76,6 +77,7 @@ ENTRY(tegra_resume)
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orr r1, r1, #1
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str r1, [r0]
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#endif
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bl tegra_resume_trusted_foundations
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#ifdef CONFIG_CACHE_L2X0
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/* L2 cache resume & re-enable */
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@ -88,6 +90,30 @@ end_ca9_scu_l2_resume:
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b cpu_resume
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ENDPROC(tegra_resume)
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/*
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* tegra_resume_trusted_foundations
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*
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* Trusted Foundations firmware initialization.
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*
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* Doesn't return if firmware presents.
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* Corrupted registers: r1, r2
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*/
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ENTRY(tegra_resume_trusted_foundations)
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/* Check whether Trusted Foundations firmware presents. */
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mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
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ldr r1, =__tegra_cpu_reset_handler_data_offset + \
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RESET_DATA(TF_PRESENT)
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ldr r1, [r2, r1]
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cmp r1, #0
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reteq lr
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.arch_extension sec
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/* First call after suspend wakes firmware. No arguments required. */
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smc #0
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b cpu_resume
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ENDPROC(tegra_resume_trusted_foundations)
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#endif
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.align L1_CACHE_SHIFT
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@ -49,8 +49,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
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/* Disable the D-cache */
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mrc p15, 0, r2, c1, c0, 0
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tst r2, #CR_C @ see tegra_sleep_cpu()
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bic r2, r2, #CR_C
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mcr p15, 0, r2, c1, c0, 0
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mcrne p15, 0, r2, c1, c0, 0
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isb
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/* Flush the D-cache */
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@ -132,10 +133,13 @@ ENTRY(tegra_shut_off_mmu)
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#ifdef CONFIG_CACHE_L2X0
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/* Disable L2 cache */
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check_cpu_part_num 0xc09, r9, r10
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movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
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movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
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moveq r3, #0
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streq r3, [r2, #L2X0_CTRL]
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retne r0
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mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
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ldr r3, [r2, #L2X0_CTRL]
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tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
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mov r3, #0
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strne r3, [r2, #L2X0_CTRL]
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#endif
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ret r0
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ENDPROC(tegra_shut_off_mmu)
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