powerpc/mm: Make some of the PGTABLE_RANGE dependency explicit
slice array size and slice mask size depend on PGTABLE_RANGE. Reviewed-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>hifive-unleashed-5.1
Aneesh Kumar K.V
Benjamin Herrenschmidt
parent
f033d659c3
commit
78f1dbde9f
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@ -15,6 +15,13 @@
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#include <asm/asm-compat.h>
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#include <asm/page.h>
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/*
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* This is necessary to get the definition of PGTABLE_RANGE which we
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* need for various slices related matters. Note that this isn't the
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* complete pgtable.h but only a portion of it.
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*/
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#include <asm/pgtable-ppc64.h>
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/*
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* Segment table
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*/
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@ -414,6 +421,8 @@ extern void slb_set_size(u16 size);
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srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
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add rt,rt,rx
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/* 4 bits per slice and we have one slice per 1TB */
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#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
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#ifndef __ASSEMBLY__
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@ -458,11 +467,7 @@ typedef struct {
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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/*
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* Right now we support 64TB and 4 bits for each
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* 1TB slice we need 32 bytes for 64TB.
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*/
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unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
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#else
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u16 sllp; /* SLB page size encoding */
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#endif
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@ -146,6 +146,15 @@ extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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extern u64 ppc64_rma_size;
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#endif /* CONFIG_PPC64 */
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struct mm_struct;
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#ifdef CONFIG_DEBUG_VM
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extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
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#else /* CONFIG_DEBUG_VM */
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static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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}
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#endif /* !CONFIG_DEBUG_VM */
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#endif /* !__ASSEMBLY__ */
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/* The kernel use the constants below to index in the page sizes array.
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@ -78,14 +78,18 @@ extern u64 ppc64_pft_size;
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#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
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#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
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/*
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* 1 bit per slice and we have one slice per 1TB
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* Right now we support only 64TB.
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* IF we change this we will have to change the type
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* of high_slices
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*/
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#define SLICE_MASK_SIZE 8
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#ifndef __ASSEMBLY__
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struct slice_mask {
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u16 low_slices;
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/*
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* This should be derived out of PGTABLE_RANGE. For the current
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* max 64TB, u64 should be ok.
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*/
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u64 high_slices;
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};
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@ -21,17 +21,6 @@
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#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
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/* Some sanity checking */
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#if TASK_SIZE_USER64 > PGTABLE_RANGE
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#error TASK_SIZE_USER64 exceeds pagetable range
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#endif
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#ifdef CONFIG_PPC_STD_MMU_64
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#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
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#error TASK_SIZE_USER64 exceeds user VSID range
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#endif
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#endif
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/*
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* Define the address range of the kernel non-linear virtual area
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*/
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@ -117,9 +106,6 @@
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#ifndef __ASSEMBLY__
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#include <linux/stddef.h>
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#include <asm/tlbflush.h>
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/*
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* This is the default implementation of various PTE accessors, it's
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* used in all cases except Book3S with 64K pages where we have a
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@ -198,7 +184,8 @@
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/* to find an entry in a kernel page-table-directory */
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/* This now only contains the vmalloc pages */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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/* Atomic PTE updates */
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static inline unsigned long pte_update(struct mm_struct *mm,
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@ -9,14 +9,6 @@
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struct mm_struct;
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#ifdef CONFIG_DEBUG_VM
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extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
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#else /* CONFIG_DEBUG_VM */
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static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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}
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#endif /* !CONFIG_DEBUG_VM */
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#endif /* !__ASSEMBLY__ */
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#if defined(CONFIG_PPC64)
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@ -27,6 +19,8 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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#ifndef __ASSEMBLY__
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#include <asm/tlbflush.h>
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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@ -103,9 +103,6 @@ DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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@ -55,8 +55,18 @@
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#include "mmu_decl.h"
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unsigned long ioremap_bot = IOREMAP_BASE;
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/* Some sanity checking */
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#if TASK_SIZE_USER64 > PGTABLE_RANGE
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#error TASK_SIZE_USER64 exceeds pagetable range
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#endif
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#ifdef CONFIG_PPC_STD_MMU_64
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#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
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#error TASK_SIZE_USER64 exceeds user VSID range
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#endif
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#endif
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unsigned long ioremap_bot = IOREMAP_BASE;
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#ifdef CONFIG_PPC_MMU_NOHASH
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static void *early_alloc_pgtable(unsigned long size)
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@ -34,6 +34,11 @@
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#include <asm/mmu.h>
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#include <asm/spu.h>
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/* some sanity checks */
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#if (PGTABLE_RANGE >> 43) > SLICE_MASK_SIZE
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#error PGTABLE_RANGE exceeds slice_mask high_slices size
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#endif
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static DEFINE_SPINLOCK(slice_convert_lock);
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