clk: imx8mq: Fix sys3 pll references
The "sys3_pll2_out" CLK was removed in refactoring so all references
need to be updated to "sys3_pll_out"
Fixes: e9dda4af68 ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
alistair/sunxi64-5.4-dsi
Leonard Crestez
Shawn Guo
parent
e8760d8a69
commit
78f5666c18
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@ -41,34 +41,34 @@ static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
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/* CCM ROOT */
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static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
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"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
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"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
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static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
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"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
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"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
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static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
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"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
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static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
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static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
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"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
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static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
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"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
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"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
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static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
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"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
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"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
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static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
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"sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
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"sys1_pll_133m", "sys3_pll_out", "sys2_pll_250m", "audio_pll1_out", };
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static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
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static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
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static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
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static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
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static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out",
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static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out",
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"sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
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static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
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@ -77,53 +77,53 @@ static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m",
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static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
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"sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
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static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
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static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
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"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
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static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
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"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
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static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_500m",
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"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
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static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll_out", "sys2_pll_333m", "sys2_pll_200m",
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"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
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static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
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"sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
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"sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
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static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
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"sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
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"sys2_pll_166m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
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static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
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"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"};
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"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out"};
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static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
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"sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
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static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
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"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
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"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
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static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
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static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
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static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
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static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
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static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
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static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
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static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
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static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
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static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
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"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
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"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
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static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
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"clk_ext3", "clk_ext4", };
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static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
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static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
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"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
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static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
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static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
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static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
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static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
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static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
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@ -151,40 +151,40 @@ static const char * const imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "
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"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
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"audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
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"audio_pll2_out", "sys3_pll_out", "sys2_pll_250m", "video_pll1_out", };
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static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
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static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
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static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
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"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
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static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
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static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
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static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
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static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
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static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
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static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
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static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
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static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
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static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
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"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
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"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
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static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
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"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
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"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
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"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
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static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
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"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
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"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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@ -196,79 +196,79 @@ static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1
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"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
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static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
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"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
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"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
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static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
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"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
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"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
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static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
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"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
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"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
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static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
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"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
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"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
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static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
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"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
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||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
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|
||||
static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
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||||
"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
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static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
|
||||
"sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
|
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|
||||
static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
|
||||
"sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
"sys2_pll_125m", "sys3_pll_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll_out", "sys2_pll_200m",
|
||||
"sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
|
||||
"clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
|
||||
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m",
|
||||
"audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", };
|
||||
static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
|
||||
"sys3_pll2_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
"sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue