drm/radeon: add accessors of pif_phy indirect register space
Required for accessing certain pcie related registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -29,6 +29,11 @@
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#define TN_SMC_IND_DATA_0 0x204
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#define TN_SMC_IND_DATA_0 0x204
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/* evergreen */
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/* evergreen */
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#define EVERGREEN_PIF_PHY0_INDEX 0x8
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#define EVERGREEN_PIF_PHY0_DATA 0xc
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#define EVERGREEN_PIF_PHY1_INDEX 0x10
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#define EVERGREEN_PIF_PHY1_DATA 0x14
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
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#define EVERGREEN_D3VGA_CONTROL 0x3e0
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#define EVERGREEN_D3VGA_CONTROL 0x3e0
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@ -2087,6 +2087,10 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
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#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
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#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
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#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
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#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
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#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
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#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
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#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
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#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
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#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
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#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
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#define WREG32_P(reg, val, mask) \
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#define WREG32_P(reg, val, mask) \
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do { \
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do { \
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uint32_t tmp_ = RREG32(reg); \
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uint32_t tmp_ = RREG32(reg); \
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@ -2173,6 +2177,36 @@ static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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WREG32(EVERGREEN_CG_IND_DATA, (v));
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WREG32(EVERGREEN_CG_IND_DATA, (v));
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}
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}
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static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
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{
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u32 r;
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WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
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r = RREG32(EVERGREEN_PIF_PHY0_DATA);
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return r;
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}
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static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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{
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WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
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WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
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}
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static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
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{
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u32 r;
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WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
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r = RREG32(EVERGREEN_PIF_PHY1_DATA);
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return r;
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}
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static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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{
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WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
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WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
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}
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void r100_pll_errata_after_index(struct radeon_device *rdev);
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void r100_pll_errata_after_index(struct radeon_device *rdev);
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