drm/nv40: implement support for on-chip PCIEGART
v2. moved nv44 pciegart table back to instmem, where it's not
accessible by userspace clients.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
hifive-unleashed-5.1
Ben Skeggs
parent
58e6c7a918
commit
7948758d27
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@ -699,6 +699,13 @@ struct drm_nouveau_private {
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uint64_t aper_size;
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uint64_t aper_free;
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struct ttm_backend_func *func;
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struct {
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struct page *page;
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dma_addr_t addr;
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} dummy;
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struct nouveau_gpuobj *sg_ctxdma;
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struct nouveau_vma vma;
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} gart_info;
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@ -164,6 +164,213 @@ static struct ttm_backend_func nv04_sgdma_backend = {
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.destroy = nouveau_sgdma_destroy
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};
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static void
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nv41_sgdma_flush(struct nouveau_sgdma_be *nvbe)
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{
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struct drm_device *dev = nvbe->dev;
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nv_wr32(dev, 0x100810, 0x00000022);
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if (!nv_wait(dev, 0x100810, 0x00000100, 0x00000100))
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NV_ERROR(dev, "vm flush timeout: 0x%08x\n",
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nv_rd32(dev, 0x100810));
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nv_wr32(dev, 0x100810, 0x00000000);
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}
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static int
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nv41_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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dma_addr_t *list = nvbe->pages;
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u32 pte = mem->start << 2;
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u32 cnt = nvbe->nr_pages;
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nvbe->offset = mem->start << PAGE_SHIFT;
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while (cnt--) {
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nv_wo32(pgt, pte, (*list++ >> 7) | 1);
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pte += 4;
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}
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nv41_sgdma_flush(nvbe);
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nvbe->bound = true;
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return 0;
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}
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static int
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nv41_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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u32 pte = (nvbe->offset >> 12) << 2;
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u32 cnt = nvbe->nr_pages;
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while (cnt--) {
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nv_wo32(pgt, pte, 0x00000000);
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pte += 4;
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}
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nv41_sgdma_flush(nvbe);
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv41_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv41_sgdma_bind,
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.unbind = nv41_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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static void
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nv44_sgdma_flush(struct nouveau_sgdma_be *nvbe)
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{
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struct drm_device *dev = nvbe->dev;
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nv_wr32(dev, 0x100814, (nvbe->nr_pages - 1) << 12);
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nv_wr32(dev, 0x100808, nvbe->offset | 0x20);
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if (!nv_wait(dev, 0x100808, 0x00000001, 0x00000001))
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NV_ERROR(dev, "gart flush timeout: 0x%08x\n",
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nv_rd32(dev, 0x100808));
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nv_wr32(dev, 0x100808, 0x00000000);
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}
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static void
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nv44_sgdma_fill(struct nouveau_gpuobj *pgt, dma_addr_t *list, u32 base, u32 cnt)
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{
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struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
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dma_addr_t dummy = dev_priv->gart_info.dummy.addr;
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u32 pte, tmp[4];
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pte = base >> 2;
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base &= ~0x0000000f;
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tmp[0] = nv_ro32(pgt, base + 0x0);
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tmp[1] = nv_ro32(pgt, base + 0x4);
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tmp[2] = nv_ro32(pgt, base + 0x8);
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tmp[3] = nv_ro32(pgt, base + 0xc);
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while (cnt--) {
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u32 addr = list ? (*list++ >> 12) : (dummy >> 12);
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switch (pte++ & 0x3) {
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case 0:
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tmp[0] &= ~0x07ffffff;
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tmp[0] |= addr;
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break;
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case 1:
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tmp[0] &= ~0xf8000000;
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tmp[0] |= addr << 27;
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tmp[1] &= ~0x003fffff;
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tmp[1] |= addr >> 5;
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break;
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case 2:
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tmp[1] &= ~0xffc00000;
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tmp[1] |= addr << 22;
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tmp[2] &= ~0x0001ffff;
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tmp[2] |= addr >> 10;
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break;
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case 3:
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tmp[2] &= ~0xfffe0000;
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tmp[2] |= addr << 17;
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tmp[3] &= ~0x00000fff;
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tmp[3] |= addr >> 15;
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break;
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}
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}
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tmp[3] |= 0x40000000;
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nv_wo32(pgt, base + 0x0, tmp[0]);
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nv_wo32(pgt, base + 0x4, tmp[1]);
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nv_wo32(pgt, base + 0x8, tmp[2]);
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nv_wo32(pgt, base + 0xc, tmp[3]);
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}
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static int
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nv44_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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dma_addr_t *list = nvbe->pages;
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u32 pte = mem->start << 2, tmp[4];
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u32 cnt = nvbe->nr_pages;
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int i;
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nvbe->offset = mem->start << PAGE_SHIFT;
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if (pte & 0x0000000c) {
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u32 max = 4 - ((pte >> 2) & 0x3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_sgdma_fill(pgt, list, pte, part);
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pte += (part << 2);
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list += part;
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cnt -= part;
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}
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while (cnt >= 4) {
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for (i = 0; i < 4; i++)
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tmp[i] = *list++ >> 12;
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nv_wo32(pgt, pte + 0x0, tmp[0] >> 0 | tmp[1] << 27);
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nv_wo32(pgt, pte + 0x4, tmp[1] >> 5 | tmp[2] << 22);
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nv_wo32(pgt, pte + 0x8, tmp[2] >> 10 | tmp[3] << 17);
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nv_wo32(pgt, pte + 0xc, tmp[3] >> 15 | 0x40000000);
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pte += 0x10;
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cnt -= 4;
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}
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if (cnt)
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nv44_sgdma_fill(pgt, list, pte, cnt);
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nv44_sgdma_flush(nvbe);
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nvbe->bound = true;
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return 0;
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}
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static int
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nv44_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *pgt = dev_priv->gart_info.sg_ctxdma;
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u32 pte = (nvbe->offset >> 12) << 2;
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u32 cnt = nvbe->nr_pages;
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if (pte & 0x0000000c) {
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u32 max = 4 - ((pte >> 2) & 0x3);
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u32 part = (cnt > max) ? max : cnt;
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nv44_sgdma_fill(pgt, NULL, pte, part);
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pte += (part << 2);
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cnt -= part;
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}
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while (cnt >= 4) {
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nv_wo32(pgt, pte + 0x0, 0x00000000);
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nv_wo32(pgt, pte + 0x4, 0x00000000);
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nv_wo32(pgt, pte + 0x8, 0x00000000);
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nv_wo32(pgt, pte + 0xc, 0x00000000);
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pte += 0x10;
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cnt -= 4;
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}
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if (cnt)
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nv44_sgdma_fill(pgt, NULL, pte, cnt);
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nv44_sgdma_flush(nvbe);
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nvbe->bound = false;
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return 0;
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}
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static struct ttm_backend_func nv44_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nv44_sgdma_bind,
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.unbind = nv44_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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static int
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nv50_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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@ -213,10 +420,7 @@ nouveau_sgdma_init_ttm(struct drm_device *dev)
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nvbe->dev = dev;
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if (dev_priv->card_type >= NV_50)
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nvbe->backend.func = &nv50_sgdma_backend;
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else
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nvbe->backend.func = &nv04_sgdma_backend;
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nvbe->backend.func = dev_priv->gart_info.func;
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return &nvbe->backend;
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}
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@ -225,31 +429,71 @@ nouveau_sgdma_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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uint32_t aper_size, obj_size;
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int i, ret;
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u32 aper_size, align;
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int ret;
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if (dev_priv->card_type >= NV_50 ||
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dev_priv->ramin_rsvd_vram >= 2 * 1024 * 1024)
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aper_size = 512 * 1024 * 1024;
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else
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aper_size = 64 * 1024 * 1024;
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/* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
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* christmas. The cards before it have them, the cards after
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* it have them, why is NV44 so unloved?
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*/
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dev_priv->gart_info.dummy.page = alloc_page(GFP_DMA32 | GFP_KERNEL);
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if (!dev_priv->gart_info.dummy.page)
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return -ENOMEM;
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dev_priv->gart_info.dummy.addr =
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pci_map_page(dev->pdev, dev_priv->gart_info.dummy.page,
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0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, dev_priv->gart_info.dummy.addr)) {
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NV_ERROR(dev, "error mapping dummy page\n");
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__free_page(dev_priv->gart_info.dummy.page);
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dev_priv->gart_info.dummy.page = NULL;
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return -ENOMEM;
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}
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if (dev_priv->card_type >= NV_50) {
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ret = nouveau_vm_get(dev_priv->chan_vm, 512 * 1024 * 1024,
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ret = nouveau_vm_get(dev_priv->chan_vm, aper_size,
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12, NV_MEM_ACCESS_RW,
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&dev_priv->gart_info.vma);
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if (ret)
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return ret;
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dev_priv->gart_info.aper_base = dev_priv->gart_info.vma.offset;
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dev_priv->gart_info.aper_size = 512 * 1024 * 1024;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.type = NOUVEAU_GART_HW;
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dev_priv->gart_info.func = &nv50_sgdma_backend;
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} else
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if (drm_pci_device_is_pcie(dev) &&
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dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) {
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if (nv44_graph_class(dev)) {
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dev_priv->gart_info.func = &nv44_sgdma_backend;
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align = 512 * 1024;
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} else {
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dev_priv->gart_info.func = &nv41_sgdma_backend;
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align = 16;
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}
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ret = nouveau_gpuobj_new(dev, NULL, aper_size / 1024, align,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj);
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if (ret) {
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NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.sg_ctxdma = gpuobj;
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.type = NOUVEAU_GART_HW;
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} else {
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if(dev_priv->ramin_rsvd_vram < 2 * 1024 * 1024)
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aper_size = 64 * 1024 * 1024;
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else
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aper_size = 512 * 1024 * 1024;
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obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4;
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obj_size += 8; /* ctxdma header */
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ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj);
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ret = nouveau_gpuobj_new(dev, NULL, (aper_size / 1024) + 8, 16,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj);
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if (ret) {
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NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
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return ret;
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@ -261,13 +505,12 @@ nouveau_sgdma_init(struct drm_device *dev)
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(0 << 14) /* RW */ |
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(2 << 16) /* PCI */);
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nv_wo32(gpuobj, 4, aper_size - 1);
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for (i = 2; i < 2 + (aper_size >> 12); i++)
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nv_wo32(gpuobj, i * 4, 0x00000000);
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dev_priv->gart_info.sg_ctxdma = gpuobj;
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.type = NOUVEAU_GART_PDMA;
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dev_priv->gart_info.func = &nv04_sgdma_backend;
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}
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return 0;
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@ -280,6 +523,13 @@ nouveau_sgdma_takedown(struct drm_device *dev)
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nouveau_gpuobj_ref(NULL, &dev_priv->gart_info.sg_ctxdma);
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nouveau_vm_put(&dev_priv->gart_info.vma);
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if (dev_priv->gart_info.dummy.page) {
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pci_unmap_page(dev->pdev, dev_priv->gart_info.dummy.addr,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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__free_page(dev_priv->gart_info.dummy.page);
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dev_priv->gart_info.dummy.page = NULL;
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}
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}
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uint32_t
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@ -24,6 +24,53 @@ nv40_fb_set_tile_region(struct drm_device *dev, int i)
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}
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}
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static void
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nv40_fb_init_gart(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
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if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
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nv_wr32(dev, 0x100800, 0x00000001);
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return;
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}
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nv_wr32(dev, 0x100800, gart->pinst | 0x00000002);
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nv_mask(dev, 0x10008c, 0x00000100, 0x00000100);
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nv_wr32(dev, 0x100820, 0x00000000);
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}
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static void
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nv44_fb_init_gart(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
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u32 vinst;
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if (dev_priv->gart_info.type != NOUVEAU_GART_HW) {
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nv_wr32(dev, 0x100850, 0x80000000);
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nv_wr32(dev, 0x100800, 0x00000001);
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return;
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}
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/* calculate vram address of this PRAMIN block, object
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* must be allocated on 512KiB alignment, and not exceed
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* a total size of 512KiB for this to work correctly
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*/
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vinst = nv_rd32(dev, 0x10020c);
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vinst -= ((gart->pinst >> 19) + 1) << 19;
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nv_wr32(dev, 0x100850, 0x80000000);
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nv_wr32(dev, 0x100818, dev_priv->gart_info.dummy.addr);
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nv_wr32(dev, 0x100804, dev_priv->gart_info.aper_size);
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nv_wr32(dev, 0x100850, 0x00008000);
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nv_mask(dev, 0x10008c, 0x00000200, 0x00000200);
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nv_wr32(dev, 0x100820, 0x00000000);
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nv_wr32(dev, 0x10082c, 0x00000001);
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nv_wr32(dev, 0x100800, vinst | 0x00000010);
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}
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int
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nv40_fb_init(struct drm_device *dev)
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{
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@ -32,12 +79,12 @@ nv40_fb_init(struct drm_device *dev)
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uint32_t tmp;
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int i;
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/* This is strictly a NV4x register (don't know about NV5x). */
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/* The blob sets these to all kinds of values, and they mess up our setup. */
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/* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
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/* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
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/* Any idea what this is? */
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nv_wr32(dev, NV40_PFB_UNK_800, 0x1);
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if (dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) {
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if (nv44_graph_class(dev))
|
||||
nv44_fb_init_gart(dev);
|
||||
else
|
||||
nv40_fb_init_gart(dev);
|
||||
}
|
||||
|
||||
switch (dev_priv->chipset) {
|
||||
case 0x40:
|
||||
|
|
|
|||
Loading…
Reference in New Issue