mmc: atmel-mci: add pdc support and runtime capabilities detection
Add pdc support for atmel-mci. It makes at91-mci driver useless because it was only used for the old atmel MCI core which has pdc but no dma support. To allow removing at91-mci, the capabilities of the MCI core are detected at runtime -- then the driver will use pio, pdc or dma transfers. Warning: at91rm9200 is not supported, to support it we need to use swab32 on data but I have no board to test it. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Chris Ball <cjb@laptop.org>hifive-unleashed-5.1
Ludovic Desroches
Chris Ball
parent
b9867f371c
commit
796211b795
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@ -88,8 +88,14 @@
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# define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */
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# define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
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# define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
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# define ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */
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# define ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */
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# define ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
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# define ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
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# define ATMCI_SDIOWAIT ( 1 << 12) /* SDIO Read Wait Operation Status */
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# define ATMCI_CSRCV ( 1 << 13) /* CE-ATA Completion Signal Received */
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# define ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */
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# define ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */
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# define ATMCI_RINDE ( 1 << 16) /* Response Index Error */
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# define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */
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# define ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */
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@ -97,6 +103,13 @@
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# define ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */
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# define ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */
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# define ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */
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# define ATMCI_CSTOE ( 1 << 23) /* Completion Signal Time-out Error */
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# define ATMCI_BLKOVRE ( 1 << 24) /* DMA Block Overrun Error */
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# define ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */
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# define ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */
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# define ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */
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# define ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */
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# define ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */
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# define ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */
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# define ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */
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#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
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@ -114,6 +127,7 @@
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#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
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# define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
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# define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
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#define ATMCI_VERSION 0x00FC /* Version */
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#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
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/* This is not including the FIFO Aperture on MCI2 */
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@ -30,6 +30,7 @@
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#include <mach/atmel-mci.h>
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#include <linux/atmel-mci.h>
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#include <linux/atmel_pdc.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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@ -58,18 +59,35 @@ enum atmel_mci_state {
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STATE_DATA_ERROR,
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};
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enum atmci_xfer_dir {
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XFER_RECEIVE = 0,
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XFER_TRANSMIT,
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};
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enum atmci_pdc_buf {
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PDC_FIRST_BUF = 0,
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PDC_SECOND_BUF,
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};
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struct atmel_mci_caps {
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bool has_dma;
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bool has_pdc;
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bool has_cfg_reg;
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bool has_cstor_reg;
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bool has_highspeed;
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bool has_rwproof;
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};
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struct atmel_mci_dma {
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#ifdef CONFIG_MMC_ATMELMCI_DMA
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struct dma_chan *chan;
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struct dma_async_tx_descriptor *data_desc;
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#endif
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};
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/**
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* struct atmel_mci - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @regs: Pointer to MMIO registers.
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* @sg: Scatterlist entry currently being processed by PIO code, if any.
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* @sg: Scatterlist entry currently being processed by PIO or PDC code.
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* @pio_offset: Offset into the current scatterlist entry.
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* @cur_slot: The slot which is currently using the controller.
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* @mrq: The request currently being processed on @cur_slot,
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@ -77,6 +95,7 @@ struct atmel_mci_dma {
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @data_size: just data->blocks * data->blksz.
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* @dma: DMA client state.
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* @data_chan: DMA channel being used for the current data transfer.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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@ -103,6 +122,13 @@ struct atmel_mci_dma {
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* @mck: The peripheral bus clock hooked up to the MMC controller.
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* @pdev: Platform device associated with the MMC controller.
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* @slot: Slots sharing this MMC controller.
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* @caps: MCI capabilities depending on MCI version.
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* @prepare_data: function to setup MCI before data transfer which
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* depends on MCI capabilities.
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* @submit_data: function to start data transfer which depends on MCI
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* capabilities.
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* @stop_transfer: function to stop data transfer which depends on MCI
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* capabilities.
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*
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* Locking
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* =======
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@ -143,6 +169,7 @@ struct atmel_mci {
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned int data_size;
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struct atmel_mci_dma dma;
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struct dma_chan *data_chan;
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@ -167,6 +194,12 @@ struct atmel_mci {
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struct platform_device *pdev;
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struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
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struct atmel_mci_caps caps;
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u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
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void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
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void (*stop_transfer)(struct atmel_mci *host);
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};
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/**
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@ -219,31 +252,6 @@ struct atmel_mci_slot {
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#define atmci_set_pending(host, event) \
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set_bit(event, &host->pending_events)
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/*
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* Enable or disable features/registers based on
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* whether the processor supports them
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*/
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static bool atmci_has_rwproof(void)
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{
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if (cpu_is_at91sam9261() || cpu_is_at91rm9200())
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return false;
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else
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return true;
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}
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/*
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* The new MCI2 module isn't 100% compatible with the old MCI module,
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* and it has a few nice features which we want to use...
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*/
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static inline bool atmci_is_mci2(void)
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{
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if (cpu_is_at91sam9g45())
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return true;
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return false;
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}
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/*
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* The debugfs stuff below is mostly optimized away when
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* CONFIG_DEBUG_FS is not set.
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@ -379,7 +387,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
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buf[ATMCI_BLKR / 4],
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buf[ATMCI_BLKR / 4] & 0xffff,
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(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
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if (atmci_is_mci2())
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if (host->caps.has_cstor_reg)
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seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
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/* Don't read RSPR and RDR; it will consume the data there */
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@ -387,7 +395,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
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atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
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atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
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if (atmci_is_mci2()) {
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if (host->caps.has_dma) {
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u32 val;
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val = buf[ATMCI_DMA / 4];
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@ -396,6 +404,9 @@ static int atmci_regs_show(struct seq_file *s, void *v)
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((val >> 4) & 3) ?
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1 << (((val >> 4) & 3) + 1) : 1,
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val & ATMCI_DMAEN ? " DMAEN" : "");
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}
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if (host->caps.has_cfg_reg) {
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u32 val;
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val = buf[ATMCI_CFG / 4];
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seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
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@ -574,33 +585,109 @@ static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
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atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
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}
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#ifdef CONFIG_MMC_ATMELMCI_DMA
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static void atmci_dma_cleanup(struct atmel_mci *host)
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/*
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* Configure given PDC buffer taking care of alignement issues.
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* Update host->data_size and host->sg.
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*/
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static void atmci_pdc_set_single_buf(struct atmel_mci *host,
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enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
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{
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struct mmc_data *data = host->data;
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u32 pointer_reg, counter_reg;
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if (data)
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dma_unmap_sg(host->dma.chan->device->dev,
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data->sg, data->sg_len,
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((data->flags & MMC_DATA_WRITE)
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? DMA_TO_DEVICE : DMA_FROM_DEVICE));
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if (dir == XFER_RECEIVE) {
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pointer_reg = ATMEL_PDC_RPR;
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counter_reg = ATMEL_PDC_RCR;
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} else {
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pointer_reg = ATMEL_PDC_TPR;
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counter_reg = ATMEL_PDC_TCR;
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}
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if (buf_nb == PDC_SECOND_BUF) {
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pointer_reg += 0x10;
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counter_reg += 0x10;
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}
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atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
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if (host->data_size <= PAGE_SIZE) {
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if (host->data_size & 0x3) {
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/* If size is different from modulo 4, transfer bytes */
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atmci_writel(host, counter_reg, host->data_size);
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atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
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} else {
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/* Else transfer 32-bits words */
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atmci_writel(host, counter_reg, host->data_size / 4);
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}
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host->data_size = 0;
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} else {
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/* We assume the size of a page is 32-bits aligned */
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atmci_writel(host, counter_reg, PAGE_SIZE / 4);
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host->data_size -= PAGE_SIZE;
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if (host->data_size)
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host->sg = sg_next(host->sg);
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}
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}
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static void atmci_stop_dma(struct atmel_mci *host)
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/*
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* Configure PDC buffer according to the data size ie configuring one or two
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* buffers. Don't use this function if you want to configure only the second
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* buffer. In this case, use atmci_pdc_set_single_buf.
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*/
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static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
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{
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struct dma_chan *chan = host->data_chan;
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atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
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if (host->data_size)
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atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
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}
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if (chan) {
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dmaengine_terminate_all(chan);
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atmci_dma_cleanup(host);
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} else {
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/* Data transfer was stopped by the interrupt handler */
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/*
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* Unmap sg lists, called when transfer is finished.
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*/
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static void atmci_pdc_cleanup(struct atmel_mci *host)
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{
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struct mmc_data *data = host->data;
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if (data)
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dma_unmap_sg(&host->pdev->dev,
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data->sg, data->sg_len,
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((data->flags & MMC_DATA_WRITE)
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? DMA_TO_DEVICE : DMA_FROM_DEVICE));
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}
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/*
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* Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
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* having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
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* interrupt needed for both transfer directions.
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*/
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static void atmci_pdc_complete(struct atmel_mci *host)
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{
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atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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atmci_pdc_cleanup(host);
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/*
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* If the card was removed, data will be NULL. No point trying
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* to send the stop command or waiting for NBUSY in this case.
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*/
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if (host->data) {
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atmci_set_pending(host, EVENT_XFER_COMPLETE);
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tasklet_schedule(&host->tasklet);
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atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
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}
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}
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/* This function is called by the DMA driver from tasklet context. */
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static void atmci_dma_cleanup(struct atmel_mci *host)
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{
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struct mmc_data *data = host->data;
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if (data)
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dma_unmap_sg(host->dma.chan->device->dev,
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data->sg, data->sg_len,
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((data->flags & MMC_DATA_WRITE)
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? DMA_TO_DEVICE : DMA_FROM_DEVICE));
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}
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/*
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* This function is called by the DMA driver from tasklet context.
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*/
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static void atmci_dma_complete(void *arg)
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{
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struct atmel_mci *host = arg;
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@ -608,7 +695,7 @@ static void atmci_dma_complete(void *arg)
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dev_vdbg(&host->pdev->dev, "DMA complete\n");
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if (atmci_is_mci2())
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if (host->caps.has_dma)
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/* Disable DMA hardware handshaking on MCI */
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atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
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@ -646,7 +733,90 @@ static void atmci_dma_complete(void *arg)
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}
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}
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static int
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/*
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* Returns a mask of interrupt flags to be enabled after the whole
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* request has been prepared.
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*/
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static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
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{
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u32 iflags;
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data->error = -EINPROGRESS;
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host->sg = data->sg;
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host->data = data;
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host->data_chan = NULL;
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iflags = ATMCI_DATA_ERROR_FLAGS;
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/*
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* Errata: MMC data write operation with less than 12
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* bytes is impossible.
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*
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* Errata: MCI Transmit Data Register (TDR) FIFO
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* corruption when length is not multiple of 4.
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*/
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if (data->blocks * data->blksz < 12
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|| (data->blocks * data->blksz) & 3)
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host->need_reset = true;
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host->pio_offset = 0;
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if (data->flags & MMC_DATA_READ)
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iflags |= ATMCI_RXRDY;
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else
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iflags |= ATMCI_TXRDY;
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return iflags;
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}
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/*
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* Set interrupt flags and set block length into the MCI mode register even
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* if this value is also accessible in the MCI block register. It seems to be
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* necessary before the High Speed MCI version. It also map sg and configure
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* PDC registers.
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*/
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static u32
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atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
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{
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u32 iflags, tmp;
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unsigned int sg_len;
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enum dma_data_direction dir;
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data->error = -EINPROGRESS;
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host->data = data;
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host->sg = data->sg;
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iflags = ATMCI_DATA_ERROR_FLAGS;
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/* Enable pdc mode */
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atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
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if (data->flags & MMC_DATA_READ) {
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dir = DMA_FROM_DEVICE;
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iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
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} else {
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dir = DMA_TO_DEVICE;
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iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
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}
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/* Set BLKLEN */
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tmp = atmci_readl(host, ATMCI_MR);
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tmp &= 0x0000ffff;
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tmp |= ATMCI_BLKLEN(data->blksz);
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atmci_writel(host, ATMCI_MR, tmp);
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/* Configure PDC */
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host->data_size = data->blocks * data->blksz;
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sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
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BUG_ON(sg_len < host->data_size / PAGE_SIZE);
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if (host->data_size)
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atmci_pdc_set_both_buf(host,
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((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
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return iflags;
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}
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static u32
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atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
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{
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struct dma_chan *chan;
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|
|
@ -655,20 +825,29 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
|||
unsigned int i;
|
||||
enum dma_data_direction direction;
|
||||
unsigned int sglen;
|
||||
u32 iflags;
|
||||
|
||||
data->error = -EINPROGRESS;
|
||||
|
||||
WARN_ON(host->data);
|
||||
host->sg = NULL;
|
||||
host->data = data;
|
||||
|
||||
iflags = ATMCI_DATA_ERROR_FLAGS;
|
||||
|
||||
/*
|
||||
* We don't do DMA on "complex" transfers, i.e. with
|
||||
* non-word-aligned buffers or lengths. Also, we don't bother
|
||||
* with all the DMA setup overhead for short transfers.
|
||||
*/
|
||||
if (data->blocks * data->blksz < ATATMCI_DMA_THRESHOLD)
|
||||
return -EINVAL;
|
||||
if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
|
||||
return atmci_prepare_data(host, data);
|
||||
if (data->blksz & 3)
|
||||
return -EINVAL;
|
||||
return atmci_prepare_data(host, data);
|
||||
|
||||
for_each_sg(data->sg, sg, data->sg_len, i) {
|
||||
if (sg->offset & 3 || sg->length & 3)
|
||||
return -EINVAL;
|
||||
return atmci_prepare_data(host, data);
|
||||
}
|
||||
|
||||
/* If we don't have a channel, we can't do DMA */
|
||||
|
|
@ -679,7 +858,7 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
|||
if (!chan)
|
||||
return -ENODEV;
|
||||
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_dma)
|
||||
atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
|
||||
|
||||
if (data->flags & MMC_DATA_READ)
|
||||
|
|
@ -688,7 +867,7 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
|||
direction = DMA_TO_DEVICE;
|
||||
|
||||
sglen = dma_map_sg(chan->device->dev, data->sg,
|
||||
data->sg_len, direction);
|
||||
data->sg_len, direction);
|
||||
|
||||
desc = chan->device->device_prep_slave_sg(chan,
|
||||
data->sg, sglen, direction,
|
||||
|
|
@ -700,13 +879,32 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
|||
desc->callback = atmci_dma_complete;
|
||||
desc->callback_param = host;
|
||||
|
||||
return 0;
|
||||
return iflags;
|
||||
unmap_exit:
|
||||
dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void atmci_submit_data(struct atmel_mci *host)
|
||||
static void
|
||||
atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Start PDC according to transfer direction.
|
||||
*/
|
||||
static void
|
||||
atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
|
||||
{
|
||||
if (data->flags & MMC_DATA_READ)
|
||||
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
|
||||
else
|
||||
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
|
||||
}
|
||||
|
||||
static void
|
||||
atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
||||
{
|
||||
struct dma_chan *chan = host->data_chan;
|
||||
struct dma_async_tx_descriptor *desc = host->dma.data_desc;
|
||||
|
|
@ -717,64 +915,39 @@ static void atmci_submit_data(struct atmel_mci *host)
|
|||
}
|
||||
}
|
||||
|
||||
#else /* CONFIG_MMC_ATMELMCI_DMA */
|
||||
|
||||
static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
||||
static void atmci_stop_transfer(struct atmel_mci *host)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static void atmci_submit_data(struct atmel_mci *host) {}
|
||||
|
||||
static void atmci_stop_dma(struct atmel_mci *host)
|
||||
{
|
||||
/* Data transfer was stopped by the interrupt handler */
|
||||
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMC_ATMELMCI_DMA */
|
||||
|
||||
/*
|
||||
* Returns a mask of interrupt flags to be enabled after the whole
|
||||
* request has been prepared.
|
||||
* Stop data transfer because error(s) occured.
|
||||
*/
|
||||
static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
|
||||
static void atmci_stop_transfer_pdc(struct atmel_mci *host)
|
||||
{
|
||||
u32 iflags;
|
||||
|
||||
data->error = -EINPROGRESS;
|
||||
|
||||
WARN_ON(host->data);
|
||||
host->sg = NULL;
|
||||
host->data = data;
|
||||
|
||||
iflags = ATMCI_DATA_ERROR_FLAGS;
|
||||
if (atmci_prepare_data_dma(host, data)) {
|
||||
host->data_chan = NULL;
|
||||
|
||||
/*
|
||||
* Errata: MMC data write operation with less than 12
|
||||
* bytes is impossible.
|
||||
*
|
||||
* Errata: MCI Transmit Data Register (TDR) FIFO
|
||||
* corruption when length is not multiple of 4.
|
||||
*/
|
||||
if (data->blocks * data->blksz < 12
|
||||
|| (data->blocks * data->blksz) & 3)
|
||||
host->need_reset = true;
|
||||
|
||||
host->sg = data->sg;
|
||||
host->pio_offset = 0;
|
||||
if (data->flags & MMC_DATA_READ)
|
||||
iflags |= ATMCI_RXRDY;
|
||||
else
|
||||
iflags |= ATMCI_TXRDY;
|
||||
}
|
||||
|
||||
return iflags;
|
||||
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
||||
}
|
||||
|
||||
static void atmci_stop_transfer_dma(struct atmel_mci *host)
|
||||
{
|
||||
struct dma_chan *chan = host->data_chan;
|
||||
|
||||
if (chan) {
|
||||
dmaengine_terminate_all(chan);
|
||||
atmci_dma_cleanup(host);
|
||||
} else {
|
||||
/* Data transfer was stopped by the interrupt handler */
|
||||
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Start a request: prepare data if needed, prepare the command and activate
|
||||
* interrupts.
|
||||
*/
|
||||
static void atmci_start_request(struct atmel_mci *host,
|
||||
struct atmel_mci_slot *slot)
|
||||
{
|
||||
|
|
@ -796,7 +969,7 @@ static void atmci_start_request(struct atmel_mci *host,
|
|||
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
host->need_reset = false;
|
||||
}
|
||||
|
|
@ -824,7 +997,7 @@ static void atmci_start_request(struct atmel_mci *host,
|
|||
dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
|
||||
ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
|
||||
|
||||
iflags |= atmci_prepare_data(host, data);
|
||||
iflags |= host->prepare_data(host, data);
|
||||
}
|
||||
|
||||
iflags |= ATMCI_CMDRDY;
|
||||
|
|
@ -833,7 +1006,7 @@ static void atmci_start_request(struct atmel_mci *host,
|
|||
atmci_start_command(host, cmd, cmdflags);
|
||||
|
||||
if (data)
|
||||
atmci_submit_data(host);
|
||||
host->submit_data(host, data);
|
||||
|
||||
if (mrq->stop) {
|
||||
host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
|
||||
|
|
@ -929,7 +1102,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
clk_enable(host->mck);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
}
|
||||
|
||||
|
|
@ -960,10 +1133,10 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
* stopping the clock when the FIFO is full/empty.
|
||||
* This state is not expected to last for long.
|
||||
*/
|
||||
if (atmci_has_rwproof())
|
||||
if (host->caps.has_rwproof)
|
||||
host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
|
||||
|
||||
if (atmci_is_mci2()) {
|
||||
if (host->caps.has_cfg_reg) {
|
||||
/* setup High Speed mode in relation with card capacity */
|
||||
if (ios->timing == MMC_TIMING_SD_HS)
|
||||
host->cfg_reg |= ATMCI_CFG_HSMODE;
|
||||
|
|
@ -973,7 +1146,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
|
||||
if (list_empty(&host->queue)) {
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
} else {
|
||||
host->need_clock_update = true;
|
||||
|
|
@ -1088,7 +1261,7 @@ static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
|
|||
*/
|
||||
if (host->need_clock_update) {
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
}
|
||||
|
||||
|
|
@ -1137,7 +1310,7 @@ static void atmci_command_complete(struct atmel_mci *host,
|
|||
"command error: status=0x%08x\n", status);
|
||||
|
||||
if (cmd->data) {
|
||||
atmci_stop_dma(host);
|
||||
host->stop_transfer(host);
|
||||
host->data = NULL;
|
||||
atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
|
||||
| ATMCI_TXRDY | ATMCI_RXRDY
|
||||
|
|
@ -1195,7 +1368,7 @@ static void atmci_detect_change(unsigned long data)
|
|||
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
|
||||
host->data = NULL;
|
||||
|
|
@ -1211,7 +1384,7 @@ static void atmci_detect_change(unsigned long data)
|
|||
/* fall through */
|
||||
case STATE_SENDING_DATA:
|
||||
mrq->data->error = -ENOMEDIUM;
|
||||
atmci_stop_dma(host);
|
||||
host->stop_transfer(host);
|
||||
break;
|
||||
case STATE_DATA_BUSY:
|
||||
case STATE_DATA_ERROR:
|
||||
|
|
@ -1290,7 +1463,7 @@ static void atmci_tasklet_func(unsigned long priv)
|
|||
case STATE_SENDING_DATA:
|
||||
if (atmci_test_and_clear_pending(host,
|
||||
EVENT_DATA_ERROR)) {
|
||||
atmci_stop_dma(host);
|
||||
host->stop_transfer(host);
|
||||
if (data->stop)
|
||||
atmci_send_stop_cmd(host, data);
|
||||
state = STATE_DATA_ERROR;
|
||||
|
|
@ -1556,6 +1729,56 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
|
|||
atmci_set_pending(host, EVENT_DATA_ERROR);
|
||||
tasklet_schedule(&host->tasklet);
|
||||
}
|
||||
|
||||
if (pending & ATMCI_ENDTX) {
|
||||
atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
|
||||
if (host->data_size) {
|
||||
atmci_pdc_set_single_buf(host,
|
||||
XFER_TRANSMIT, PDC_SECOND_BUF);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
|
||||
}
|
||||
}
|
||||
|
||||
if (pending & ATMCI_TXBUFE) {
|
||||
atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
|
||||
/*
|
||||
* We can receive this interruption before having configured
|
||||
* the second pdc buffer, so we need to reconfigure first and
|
||||
* second buffers again
|
||||
*/
|
||||
if (host->data_size) {
|
||||
atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
|
||||
} else {
|
||||
atmci_pdc_complete(host);
|
||||
}
|
||||
}
|
||||
|
||||
if (pending & ATMCI_ENDRX) {
|
||||
atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
|
||||
|
||||
if (host->data_size) {
|
||||
atmci_pdc_set_single_buf(host,
|
||||
XFER_RECEIVE, PDC_SECOND_BUF);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
|
||||
}
|
||||
}
|
||||
|
||||
if (pending & ATMCI_RXBUFF) {
|
||||
atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
|
||||
/*
|
||||
* We can receive this interruption before having configured
|
||||
* the second pdc buffer, so we need to reconfigure first and
|
||||
* second buffers again
|
||||
*/
|
||||
if (host->data_size) {
|
||||
atmci_pdc_set_both_buf(host, XFER_RECEIVE);
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
|
||||
} else {
|
||||
atmci_pdc_complete(host);
|
||||
}
|
||||
}
|
||||
|
||||
if (pending & ATMCI_NOTBUSY) {
|
||||
atmci_writel(host, ATMCI_IDR,
|
||||
ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
|
||||
|
|
@ -1622,7 +1845,7 @@ static int __init atmci_init_slot(struct atmel_mci *host,
|
|||
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
if (sdio_irq)
|
||||
mmc->caps |= MMC_CAP_SDIO_IRQ;
|
||||
if (atmci_is_mci2())
|
||||
if (host->caps.has_highspeed)
|
||||
mmc->caps |= MMC_CAP_SD_HIGHSPEED;
|
||||
if (slot_data->bus_width >= 4)
|
||||
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
||||
|
|
@ -1705,7 +1928,6 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
|
|||
mmc_free_host(slot->mmc);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMC_ATMELMCI_DMA
|
||||
static bool atmci_filter(struct dma_chan *chan, void *slave)
|
||||
{
|
||||
struct mci_dma_data *sl = slave;
|
||||
|
|
@ -1747,9 +1969,60 @@ static void atmci_configure_dma(struct atmel_mci *host)
|
|||
"Using %s for DMA transfers\n",
|
||||
dma_chan_name(host->dma.chan));
|
||||
}
|
||||
|
||||
static inline unsigned int atmci_get_version(struct atmel_mci *host)
|
||||
{
|
||||
return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
|
||||
}
|
||||
|
||||
/*
|
||||
* HSMCI (High Speed MCI) module is not fully compatible with MCI module.
|
||||
* HSMCI provides DMA support and a new config register but no more supports
|
||||
* PDC.
|
||||
*/
|
||||
static void __init atmci_get_cap(struct atmel_mci *host)
|
||||
{
|
||||
unsigned int version;
|
||||
|
||||
version = atmci_get_version(host);
|
||||
dev_info(&host->pdev->dev,
|
||||
"version: 0x%x\n", version);
|
||||
|
||||
host->caps.has_dma = 0;
|
||||
host->caps.has_pdc = 0;
|
||||
host->caps.has_cfg_reg = 0;
|
||||
host->caps.has_cstor_reg = 0;
|
||||
host->caps.has_highspeed = 0;
|
||||
host->caps.has_rwproof = 0;
|
||||
|
||||
/* keep only major version number */
|
||||
switch (version & 0xf00) {
|
||||
case 0x100:
|
||||
case 0x200:
|
||||
host->caps.has_pdc = 1;
|
||||
host->caps.has_rwproof = 1;
|
||||
break;
|
||||
case 0x300:
|
||||
case 0x400:
|
||||
case 0x500:
|
||||
#ifdef CONFIG_AT_HDMAC
|
||||
host->caps.has_dma = 1;
|
||||
#else
|
||||
static void atmci_configure_dma(struct atmel_mci *host) {}
|
||||
host->caps.has_dma = 0;
|
||||
dev_info(&host->pdev->dev,
|
||||
"has dma capability but dma engine is not selected, then use pio\n");
|
||||
#endif
|
||||
host->caps.has_cfg_reg = 1;
|
||||
host->caps.has_cstor_reg = 1;
|
||||
host->caps.has_highspeed = 1;
|
||||
host->caps.has_rwproof = 1;
|
||||
break;
|
||||
default:
|
||||
dev_warn(&host->pdev->dev,
|
||||
"Unmanaged mci version, set minimum capabilities\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init atmci_probe(struct platform_device *pdev)
|
||||
{
|
||||
|
|
@ -1802,7 +2075,27 @@ static int __init atmci_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
goto err_request_irq;
|
||||
|
||||
atmci_configure_dma(host);
|
||||
/* Get MCI capabilities and set operations according to it */
|
||||
atmci_get_cap(host);
|
||||
if (host->caps.has_dma) {
|
||||
dev_info(&pdev->dev, "using DMA\n");
|
||||
host->prepare_data = &atmci_prepare_data_dma;
|
||||
host->submit_data = &atmci_submit_data_dma;
|
||||
host->stop_transfer = &atmci_stop_transfer_dma;
|
||||
} else if (host->caps.has_pdc) {
|
||||
dev_info(&pdev->dev, "using PDC\n");
|
||||
host->prepare_data = &atmci_prepare_data_pdc;
|
||||
host->submit_data = &atmci_submit_data_pdc;
|
||||
host->stop_transfer = &atmci_stop_transfer_pdc;
|
||||
} else {
|
||||
dev_info(&pdev->dev, "no DMA, no PDC\n");
|
||||
host->prepare_data = &atmci_prepare_data;
|
||||
host->submit_data = &atmci_submit_data;
|
||||
host->stop_transfer = &atmci_stop_transfer;
|
||||
}
|
||||
|
||||
if (host->caps.has_dma)
|
||||
atmci_configure_dma(host);
|
||||
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
|
|
@ -1834,10 +2127,8 @@ static int __init atmci_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
|
||||
err_init_slot:
|
||||
#ifdef CONFIG_MMC_ATMELMCI_DMA
|
||||
if (host->dma.chan)
|
||||
dma_release_channel(host->dma.chan);
|
||||
#endif
|
||||
free_irq(irq, host);
|
||||
err_request_irq:
|
||||
iounmap(host->regs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue