unicore32 core architecture: processor and system headers
This patch includes processor and system headers. System call interface is here. We used the syscall interface the same as asm-generic version. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
GuanXuetao
parent
87c1a3fb7c
commit
79725df578
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@ -0,0 +1,24 @@
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/*
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* linux/arch/unicore32/include/asm/byteorder.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* UniCore ONLY support Little Endian mode, the data bus is connected such
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* that byte accesses appear as:
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* 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
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* and word accesses (data or instruction) appear as:
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* d0...d31
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*/
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#ifndef __UNICORE_BYTEORDER_H__
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#define __UNICORE_BYTEORDER_H__
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#include <linux/byteorder/little_endian.h>
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#endif
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@ -0,0 +1,45 @@
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/*
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* linux/arch/unicore32/include/asm/cpu-single.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_CPU_SINGLE_H__
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#define __UNICORE_CPU_SINGLE_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#define cpu_switch_mm(pgd, mm) cpu_do_switch_mm(virt_to_phys(pgd), mm)
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#define cpu_get_pgd() \
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({ \
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unsigned long pg; \
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__asm__("movc %0, p0.c2, #0" \
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: "=r" (pg) : : "cc"); \
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pg &= ~0x0fff; \
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(pgd_t *)phys_to_virt(pg); \
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})
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struct mm_struct;
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/* declare all the functions as extern */
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extern void cpu_proc_fin(void);
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extern int cpu_do_idle(void);
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extern void cpu_dcache_clean_area(void *, int);
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extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
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extern void cpu_set_pte(pte_t *ptep, pte_t pte);
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extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __UNICORE_CPU_SINGLE_H__ */
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@ -0,0 +1,33 @@
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/*
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* linux/arch/unicore32/include/asm/cputype.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_CPUTYPE_H__
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#define __UNICORE_CPUTYPE_H__
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#include <linux/stringify.h>
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#define CPUID_CPUID 0
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#define CPUID_CACHETYPE 1
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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asm("movc %0, p0.c0, #" __stringify(reg) \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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#define uc32_cpuid read_cpuid(CPUID_CPUID)
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#define uc32_cachetype read_cpuid(CPUID_CACHETYPE)
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#endif
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@ -0,0 +1,32 @@
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/*
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* linux/arch/unicore32/include/asm/hwcap.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_HWCAP_H__
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#define __UNICORE_HWCAP_H__
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/*
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* HWCAP flags
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*/
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#define HWCAP_MSP 1
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#define HWCAP_UNICORE16 2
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#define HWCAP_CMOV 4
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#define HWCAP_UNICORE_F64 8
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#define HWCAP_TLS 0x80
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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/*
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* This yields a mask that user programs can use to figure out what
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* instruction set this cpu supports.
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*/
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#define ELF_HWCAP (HWCAP_CMOV | HWCAP_UNICORE_F64)
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#endif
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#endif
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@ -0,0 +1,92 @@
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/*
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* linux/arch/unicore32/include/asm/processor.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_PROCESSOR_H__
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#define __UNICORE_PROCESSOR_H__
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l; })
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#ifdef __KERNEL__
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#ifdef __KERNEL__
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#define STACK_TOP TASK_SIZE
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#define STACK_TOP_MAX TASK_SIZE
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#endif
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struct debug_entry {
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u32 address;
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u32 insn;
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};
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struct debug_info {
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int nsaved;
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struct debug_entry bp[2];
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};
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struct thread_struct {
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/* fault info */
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unsigned long address;
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unsigned long trap_no;
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unsigned long error_code;
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/* debugging */
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struct debug_info debug;
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};
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#define INIT_THREAD { }
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#define start_thread(regs, pc, sp) \
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({ \
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unsigned long *stack = (unsigned long *)sp; \
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set_fs(USER_DS); \
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memset(regs->uregs, 0, sizeof(regs->uregs)); \
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regs->UCreg_asr = USER_MODE; \
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regs->UCreg_pc = pc & ~1; /* pc */ \
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regs->UCreg_sp = sp; /* sp */ \
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regs->UCreg_02 = stack[2]; /* r2 (envp) */ \
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regs->UCreg_01 = stack[1]; /* r1 (argv) */ \
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regs->UCreg_00 = stack[0]; /* r0 (argc) */ \
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})
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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unsigned long get_wchan(struct task_struct *p);
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#define cpu_relax() barrier()
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/*
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* Create a new kernel thread
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*/
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extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->UCreg_pc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->UCreg_sp)
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#endif
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#endif /* __UNICORE_PROCESSOR_H__ */
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@ -0,0 +1,161 @@
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/*
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* linux/arch/unicore32/include/asm/system.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_SYSTEM_H__
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#define __UNICORE_SYSTEM_H__
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#ifdef __KERNEL__
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/*
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* CR1 bits (CP#0 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_D (1 << 2) /* Dcache enable */
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#define CR_I (1 << 3) /* Icache enable */
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#define CR_B (1 << 4) /* Dcache write mechanism: write back */
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#define CR_T (1 << 5) /* Burst enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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struct thread_info;
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struct task_struct;
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struct pt_regs;
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void die(const char *msg, struct pt_regs *regs, int err);
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struct siginfo;
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void uc32_notify_die(const char *str, struct pt_regs *regs,
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struct siginfo *info, unsigned long err, unsigned long trap);
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void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
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struct pt_regs *),
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int sig, int code, const char *name);
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#define xchg(ptr, x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
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extern asmlinkage void __backtrace(void);
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extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
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struct mm_struct;
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extern void show_pte(struct mm_struct *mm, unsigned long addr);
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extern void __show_regs(struct pt_regs *);
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extern int cpu_architecture(void);
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extern void cpu_init(void);
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#define vectors_high() (cr_alignment & CR_V)
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#define isb() __asm__ __volatile__ ("" : : : "memory")
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#define dsb() __asm__ __volatile__ ("" : : : "memory")
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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extern unsigned long cr_no_alignment; /* defined in entry-unicore.S */
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extern unsigned long cr_alignment; /* defined in entry-unicore.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("movc %0, p0.c1, #0" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("movc p0.c1, %0, #0 @set CR"
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: : "r" (val) : "cc");
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isb();
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}
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extern void adjust_cr(unsigned long mask, unsigned long set);
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *,
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struct thread_info *, struct thread_info *);
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extern void panic(const char *fmt, ...);
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#define switch_to(prev, next, last) \
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do { \
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last = __switch_to(prev, \
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task_thread_info(prev), task_thread_info(next)); \
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} while (0)
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static inline unsigned long
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__xchg(unsigned long x, volatile void *ptr, int size)
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{
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unsigned long ret;
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switch (size) {
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case 1:
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asm volatile("@ __xchg1\n"
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" swapb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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" swapw %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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default:
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panic("xchg: bad data size: ptr 0x%p, size %d\n",
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ptr, size);
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}
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return ret;
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}
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#include <asm-generic/cmpxchg-local.h>
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), \
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(unsigned long)(o), (unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) \
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__cmpxchg64_local_generic((ptr), (o), (n))
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#include <asm-generic/cmpxchg.h>
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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@ -0,0 +1,18 @@
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/*
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* linux/arch/unicore32/include/asm/unistd.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#if !defined(__UNICORE_UNISTD_H__) || defined(__SYSCALL)
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#define __UNICORE_UNISTD_H__
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/* Use the standard ABI for syscalls. */
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#include <asm-generic/unistd.h>
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#endif /* __UNICORE_UNISTD_H__ */
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@ -0,0 +1,126 @@
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/*
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* linux/arch/unicore32/kernel/sys.c
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*
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||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/sem.h>
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#include <linux/msg.h>
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#include <linux/shm.h>
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#include <linux/stat.h>
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#include <linux/syscalls.h>
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#include <linux/mman.h>
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#include <linux/fs.h>
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#include <linux/file.h>
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#include <linux/ipc.h>
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#include <linux/uaccess.h>
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#include <asm/syscalls.h>
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#include <asm/cacheflush.h>
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/* Clone a task - this clones the calling program thread.
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* This is called indirectly via a small wrapper
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*/
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asmlinkage long __sys_clone(unsigned long clone_flags, unsigned long newsp,
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void __user *parent_tid, void __user *child_tid,
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struct pt_regs *regs)
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{
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if (!newsp)
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newsp = regs->UCreg_sp;
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return do_fork(clone_flags, newsp, regs, 0,
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parent_tid, child_tid);
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}
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/* sys_execve() executes a new program.
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* This is called indirectly via a small wrapper
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*/
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asmlinkage long __sys_execve(const char __user *filename,
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const char __user *const __user *argv,
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const char __user *const __user *envp,
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struct pt_regs *regs)
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{
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int error;
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char *fn;
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fn = getname(filename);
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error = PTR_ERR(fn);
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if (IS_ERR(fn))
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goto out;
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error = do_execve(fn, argv, envp, regs);
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putname(fn);
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out:
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return error;
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}
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int kernel_execve(const char *filename,
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const char *const argv[],
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const char *const envp[])
|
||||
{
|
||||
struct pt_regs regs;
|
||||
int ret;
|
||||
|
||||
memset(®s, 0, sizeof(struct pt_regs));
|
||||
ret = do_execve(filename,
|
||||
(const char __user *const __user *)argv,
|
||||
(const char __user *const __user *)envp, ®s);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* Save argc to the register structure for userspace.
|
||||
*/
|
||||
regs.UCreg_00 = ret;
|
||||
|
||||
/*
|
||||
* We were successful. We won't be returning to our caller, but
|
||||
* instead to user space by manipulating the kernel stack.
|
||||
*/
|
||||
asm("add r0, %0, %1\n\t"
|
||||
"mov r1, %2\n\t"
|
||||
"mov r2, %3\n\t"
|
||||
"mov r22, #0\n\t" /* not a syscall */
|
||||
"mov r23, %0\n\t" /* thread structure */
|
||||
"b.l memmove\n\t" /* copy regs to top of stack */
|
||||
"mov sp, r0\n\t" /* reposition stack pointer */
|
||||
"b ret_to_user"
|
||||
:
|
||||
: "r" (current_thread_info()),
|
||||
"Ir" (THREAD_START_SP - sizeof(regs)),
|
||||
"r" (®s),
|
||||
"Ir" (sizeof(regs))
|
||||
: "r0", "r1", "r2", "r3", "ip", "lr", "memory");
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(kernel_execve);
|
||||
|
||||
/* Note: used by the compat code even in 64-bit Linux. */
|
||||
SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
|
||||
unsigned long, prot, unsigned long, flags,
|
||||
unsigned long, fd, unsigned long, off_4k)
|
||||
{
|
||||
return sys_mmap_pgoff(addr, len, prot, flags, fd,
|
||||
off_4k);
|
||||
}
|
||||
|
||||
/* Provide the actual syscall number to call mapping. */
|
||||
#undef __SYSCALL
|
||||
#define __SYSCALL(nr, call) [nr] = (call),
|
||||
|
||||
/* Note that we don't include <linux/unistd.h> but <asm/unistd.h> */
|
||||
void *sys_call_table[__NR_syscalls] = {
|
||||
[0 ... __NR_syscalls-1] = sys_ni_syscall,
|
||||
#include <asm/unistd.h>
|
||||
};
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* linux/arch/unicore32/mm/proc-macros.S
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* We need constants.h for:
|
||||
* VMA_VM_MM
|
||||
* VMA_VM_FLAGS
|
||||
* VM_EXEC
|
||||
*/
|
||||
#include <generated/asm-offsets.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
/*
|
||||
* the cache line sizes of the I and D cache are the same
|
||||
*/
|
||||
#define CACHE_LINESIZE 32
|
||||
|
||||
/*
|
||||
* This is the maximum size of an area which will be invalidated
|
||||
* using the single invalidate entry instructions. Anything larger
|
||||
* than this, and we go for the whole cache.
|
||||
*
|
||||
* This value should be chosen such that we choose the cheapest
|
||||
* alternative.
|
||||
*/
|
||||
#ifdef CONFIG_CPU_UCV2
|
||||
#define MAX_AREA_SIZE 0x800 /* 64 cache line */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
|
||||
*/
|
||||
.macro vma_vm_mm, rd, rn
|
||||
ldw \rd, [\rn+], #VMA_VM_MM
|
||||
.endm
|
||||
|
||||
/*
|
||||
* vma_vm_flags - get vma->vm_flags
|
||||
*/
|
||||
.macro vma_vm_flags, rd, rn
|
||||
ldw \rd, [\rn+], #VMA_VM_FLAGS
|
||||
.endm
|
||||
|
||||
.macro tsk_mm, rd, rn
|
||||
ldw \rd, [\rn+], #TI_TASK
|
||||
ldw \rd, [\rd+], #TSK_ACTIVE_MM
|
||||
.endm
|
||||
|
||||
/*
|
||||
* act_mm - get current->active_mm
|
||||
*/
|
||||
.macro act_mm, rd
|
||||
andn \rd, sp, #8128
|
||||
andn \rd, \rd, #63
|
||||
ldw \rd, [\rd+], #TI_TASK
|
||||
ldw \rd, [\rd+], #TSK_ACTIVE_MM
|
||||
.endm
|
||||
|
||||
/*
|
||||
* mmid - get context id from mm pointer (mm->context.id)
|
||||
*/
|
||||
.macro mmid, rd, rn
|
||||
ldw \rd, [\rn+], #MM_CONTEXT_ID
|
||||
.endm
|
||||
|
||||
/*
|
||||
* mask_asid - mask the ASID from the context ID
|
||||
*/
|
||||
.macro asid, rd, rn
|
||||
and \rd, \rn, #255
|
||||
.endm
|
||||
|
||||
.macro crval, clear, mmuset, ucset
|
||||
.word \clear
|
||||
.word \mmuset
|
||||
.endm
|
||||
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
/*
|
||||
* va2pa va, pa, tbl, msk, off, err
|
||||
* This macro is used to translate virtual address to its physical address.
|
||||
*
|
||||
* va: virtual address
|
||||
* pa: physical address, result is stored in this register
|
||||
* tbl, msk, off: temp registers, will be destroyed
|
||||
* err: jump to error label if the physical address not exist
|
||||
* NOTE: all regs must be different
|
||||
*/
|
||||
.macro va2pa, va, pa, tbl, msk, off, err=990f
|
||||
movc \pa, p0.c2, #0
|
||||
mov \off, \va >> #22 @ off <- index of 1st page table
|
||||
adr \tbl, 910f @ tbl <- table of 1st page table
|
||||
900: @ ---- handle 1, 2 page table
|
||||
add \pa, \pa, #PAGE_OFFSET @ pa <- virt addr of page table
|
||||
ldw \pa, [\pa+], \off << #2 @ pa <- the content of pt
|
||||
cand.a \pa, #4 @ test exist bit
|
||||
beq \err @ if not exist
|
||||
and \off, \pa, #3 @ off <- the last 2 bits
|
||||
add \tbl, \tbl, \off << #3 @ cmove table pointer
|
||||
ldw \msk, [\tbl+], #0 @ get the mask
|
||||
ldw pc, [\tbl+], #4
|
||||
930: @ ---- handle 2nd page table
|
||||
and \pa, \pa, \msk @ pa <- phys addr of 2nd pt
|
||||
mov \off, \va << #10
|
||||
cntlo \tbl, \msk @ use tbl as temp reg
|
||||
mov \off, \off >> \tbl
|
||||
mov \off, \off >> #2 @ off <- index of 2nd pt
|
||||
adr \tbl, 920f @ tbl <- table of 2nd pt
|
||||
b 900b
|
||||
910: @ 1st level page table
|
||||
.word 0xfffff000, 930b @ second level page table
|
||||
.word 0xfffffc00, 930b @ second level large page table
|
||||
.word 0x00000000, \err @ invalid
|
||||
.word 0xffc00000, 980f @ super page
|
||||
|
||||
920: @ 2nd level page table
|
||||
.word 0xfffff000, 980f @ page
|
||||
.word 0xffffc000, 980f @ middle page
|
||||
.word 0xffff0000, 980f @ large page
|
||||
.word 0x00000000, \err @ invalid
|
||||
980:
|
||||
andn \tbl, \va, \msk
|
||||
and \pa, \pa, \msk
|
||||
or \pa, \pa, \tbl
|
||||
990:
|
||||
.endm
|
||||
#endif
|
||||
|
||||
.macro dcacheline_flush, addr, t1, t2
|
||||
mov \t1, \addr << #20
|
||||
ldw \t2, =_stext @ _stext must ALIGN(4096)
|
||||
add \t2, \t2, \t1 >> #20
|
||||
ldw \t1, [\t2+], #0x0000
|
||||
ldw \t1, [\t2+], #0x1000
|
||||
ldw \t1, [\t2+], #0x2000
|
||||
ldw \t1, [\t2+], #0x3000
|
||||
.endm
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* linux/arch/unicore32/mm/proc-ucv2.S
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/hwcap.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#include "proc-macros.S"
|
||||
|
||||
ENTRY(cpu_proc_fin)
|
||||
stm.w (lr), [sp-]
|
||||
mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE
|
||||
mov.a asr, ip
|
||||
b.l __cpuc_flush_kern_all
|
||||
ldm.w (pc), [sp]+
|
||||
|
||||
/*
|
||||
* cpu_reset(loc)
|
||||
*
|
||||
* Perform a soft reset of the system. Put the CPU into the
|
||||
* same state as it would be if it had been reset, and branch
|
||||
* to what would be the reset vector.
|
||||
*
|
||||
* - loc - location to jump to for soft reset
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_reset)
|
||||
mov ip, #0
|
||||
movc p0.c5, ip, #28 @ Cache invalidate all
|
||||
nop8
|
||||
|
||||
movc p0.c6, ip, #6 @ TLB invalidate all
|
||||
nop8
|
||||
|
||||
movc ip, p0.c1, #0 @ ctrl register
|
||||
or ip, ip, #0x2000 @ vector base address
|
||||
andn ip, ip, #0x000f @ ............idam
|
||||
movc p0.c1, ip, #0 @ disable caches and mmu
|
||||
nop
|
||||
mov pc, r0 @ jump to loc
|
||||
nop8
|
||||
|
||||
/*
|
||||
* cpu_do_idle()
|
||||
*
|
||||
* Idle the processor (eg, wait for interrupt).
|
||||
*
|
||||
* IRQs are already disabled.
|
||||
*/
|
||||
ENTRY(cpu_do_idle)
|
||||
mov r0, #0 @ PCI address
|
||||
.rept 8
|
||||
ldw r1, [r0]
|
||||
.endr
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(cpu_dcache_clean_area)
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
csub.a r1, #MAX_AREA_SIZE
|
||||
bsg 101f
|
||||
mov r9, #PAGE_SZ
|
||||
sub r9, r9, #1 @ PAGE_MASK
|
||||
1: va2pa r0, r10, r11, r12, r13 @ r10 is PA
|
||||
b 3f
|
||||
2: cand.a r0, r9
|
||||
beq 1b
|
||||
3: movc p0.c5, r10, #11 @ clean D entry
|
||||
nop8
|
||||
add r0, r0, #CACHE_LINESIZE
|
||||
add r10, r10, #CACHE_LINESIZE
|
||||
sub.a r1, r1, #CACHE_LINESIZE
|
||||
bua 2b
|
||||
mov pc, lr
|
||||
#endif
|
||||
101: mov ip, #0
|
||||
movc p0.c5, ip, #10 @ Dcache clean all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* cpu_do_switch_mm(pgd_phys)
|
||||
*
|
||||
* Set the translation table base pointer to be pgd_phys
|
||||
*
|
||||
* - pgd_phys - physical address of new pgd
|
||||
*
|
||||
* It is assumed that:
|
||||
* - we are not using split page tables
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_do_switch_mm)
|
||||
movc p0.c2, r0, #0 @ update page table ptr
|
||||
nop8
|
||||
|
||||
movc p0.c6, ip, #6 @ TLB invalidate all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* cpu_set_pte(ptep, pte)
|
||||
*
|
||||
* Set a level 2 translation table entry.
|
||||
*
|
||||
* - ptep - pointer to level 2 translation table entry
|
||||
* - pte - PTE value to store
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_set_pte)
|
||||
stw r1, [r0]
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
sub r2, r0, #PAGE_OFFSET
|
||||
movc p0.c5, r2, #11 @ Dcache clean line
|
||||
nop8
|
||||
#else
|
||||
mov ip, #0
|
||||
movc p0.c5, ip, #10 @ Dcache clean all
|
||||
nop8
|
||||
@dcacheline_flush r0, r2, ip
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
Loading…
Reference in New Issue